3 ms·

While I'd agree with you that TSMC's current 7nm seems to be better than Intel's current 10nm, comparing Epyc to Ice Lake SP isnt quite the same. Intel is putti

by ac29 6y ago

While I'd agree with you that TSMC's current 7nm seems to be better than Intel's current 10nm, comparing Epyc to Ice Lake SP isnt quite the same. Intel is putting (up to) 40 cores on the same die, AMD only puts 8 cores. It looks like AMD has the better method for overall performance, and Intel will likely follow them - in addition to being able to get more cores into a socket, I suspect Intel could also crank frequency higher with less cores per die.

adrian_b 6y ago
For the user it does not matter how many cores are on a die. For the user it matters what is included in a package. The new Ice Lake Server package (77.5 mm x 56.5 mm) has finally reached about the same size as the Epyc package (75.4 mm x 58.5 mm), because now Intel offers for the first time 8 memory channels, like its competitors have offered for many years. So in packages of the same size, Intel has 40 cores, while AMD offers 64 cores. Moreover Intel requires an extra package for the I/O controller, while AMD includes it in the CPU package. So for general-purpose users, AMD offers much more in the same space. On the other hand, Ice Lake Server has twice the number of FMA units, so it has as many floating-point multipliers as 80 AMD cores. This advantage is diminished by the fact that the clock frequency for heavy AVX-512 instructions is only 80% of the nominal frequency, but it can still give an advantage to Ice Lake Server for the programs that can use AVX-512.
totalZero 6y ago
From a yield perspective, if core failures are independent events, binning is probably easier with the big chiplet approach. The Epyc 3 approach does have some drawbacks. Looking at the Epyc 3 TDP numbers, there's probably a nontrivial thermal cost to breaking out the dies as AMD has. Not to mention the I/O for Epyc 3 is not on TSMC 7nm.

3 ms·

While I'd agree with you that TSMC's current 7nm seems to be better than Intel's current 10nm, comparing Epyc to Ice Lake SP isnt quite the same. Intel is putti

by ac29 6y ago

adrian_b 6y ago
For the user it does not matter how many cores are on a die. For the user it matters what is included in a package. The new Ice Lake Server package (77.5 mm x 56.5 mm) has finally reached about the same size as the Epyc package (75.4 mm x 58.5 mm), because now Intel offers for the first time 8 memory channels, like its competitors have offered for many years. So in packages of the same size, Intel has 40 cores, while AMD offers 64 cores. Moreover Intel requires an extra package for the I/O controller, while AMD includes it in the CPU package. So for general-purpose users, AMD offers much more in the same space. On the other hand, Ice Lake Server has twice the number of FMA units, so it has as many floating-point multipliers as 80 AMD cores. This advantage is diminished by the fact that the clock frequency for heavy AVX-512 instructions is only 80% of the nominal frequency, but it can still give an advantage to Ice Lake Server for the programs that can use AVX-512.
totalZero 6y ago
From a yield perspective, if core failures are independent events, binning is probably easier with the big chiplet approach. The Epyc 3 approach does have some drawbacks. Looking at the Epyc 3 TDP numbers, there's probably a nontrivial thermal cost to breaking out the dies as AMD has. Not to mention the I/O for Epyc 3 is not on TSMC 7nm.