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Well, one idea is you could help us get a compiler up and running for our home-brew CPU project: https://github.com/hsc-latte/hs32core-rtl https://github.com/hs
by etaioinshrdlu 6y ago
Well, one idea is you could help us get a compiler up and running for our home-brew CPU project: https://github.com/hsc-latte/hs32core-rtl https://github.com/hsc-latte/hs32core-rtl
We are at the stage of lacking a lot of software help. We have an assembler, but that's it.
We're expecting some initial chips back in a few months from using the Google/Skywater/Efabless shuttle program: https://efabless.com/open_shuttle_program https://efabless.com/open_shuttle_program
Currently we are simulating the CPU in verilog simulators, as well as fpga's. There's a lot of fun very low-level work to be done.
- f00zz 6y agoHey, this is pretty cool. Did you guys consider writing a LLVM backend for your ISA? I'd love to help.
- carrot_boy 6y agodo you have experience with LLVM? you can get an idea of our ISA encodings here: https://github.com/hsc-latte/caravel-hs32core https://github.com/hsc-latte/caravel-hs32core (which is probably the better repo to flaunt)
- mindentropy 6y agoThis is real cool stuff and was wondering how I missed this. Do you need someone to write embedded tools? I am getting into FPGA for RISCV with the Arty board and was wondering if you need any help regarding this.