The professional tools are licensed at 100k-200k/year per seat each, there is no way around them if you want to actually tape out the chip. An experienced backe

The professional tools are licensed at 100k-200k/year per seat each, there is no way around them if you want to actually tape out the chip. An experienced backend engineer needs 3-4 months to take a design from Verilog to a file that can be send to a Foundry. You also need access to a PDK from a manufacturer like TSMC and probably will have to license some of the digital-analog components (PLL, IO-Pads) from someone. Manufacturing itself is fairly expensive as well, we taped out via europractice ( https://europractice-ic.com/schedules-prices/ https://europractice-ic.com/schedules-prices/), you pay about 12k per square millimetre in TSMC 65nm. Even older processes are more affordable, but you have to keep in mind that each of them requires at least some customisation and access to blocks specific to the process (memories for instance). On the design and verification side the story is slightly better, verilator (https://www.veripool.org/wiki/verilator https://www.veripool.org/wiki/verilator) for instance is an excellent tool that lets you simulate system-verilog code with high performance. It has seen wide industry adoption in the last years and now a couple of companies like Google, SiFive, etc. are investing in open source tooling for hardware. You can go a long way to building your design without having to pay for expensive licenses. The downside is that most of the interface type components (PCI-Express, DDR4, etc.) are prohibitively complicated to build yourself, so you will need to rely on external IP at some point.