Idea is to have a fairly simple synthesizeable softcore with an existing toolchain of some sort. SEU mitigation seems like it belongs at a lower abstraction le

Idea is to have a fairly simple synthesizeable softcore with an existing toolchain of some sort. SEU mitigation seems like it belongs at a lower abstraction level, the FPGA fabric itself. I'd like to hope RiscV hard macros start showing up on low end FPGA's soon, just like we have DSP and RAM blocks, so we can stop chewing up LUTs with softcores. ARM cores are on high end FPGAs now and the ARM tax must account for part of that differentiation. RiscV bypasses the tax.