2 ms·

A few years ago I was programming for a VLIW processor that had delay slots for all kinds of instructions. These were longer, however; I think the branch instru

• ajross 6y ago
  Instruction scheduling rules in VLIW are for a slightly different reason than the MIPS BDS. VLIW is designed to expose the parallel instruction dispatch capabilities to the compiler in a way that doesn't require hardware to track dependencies between them. Fundamentally you're tracking register/data dependencies, though often there is a latency minimum the compiler is expected to enforce. But the rules there are present for correctness, not performance per se. With MIPS, the problem being solved that the original 4-stage pipeline always had exactly one cycle of latency between the evaluation of a branch decision and the fetch of the next instruction. So by always executing the next instruction unconditionally they could sneak in exactly one extra instruction per branch. It was a 100% pure performance play, and actually fairly clever at the time. MIPS was frighteningly fast when it was released in ~1987, and this was one of the reasons why. ...until the second CPU. Once that pipeline gets longer, the branch prediction logic gets deeper, or instructions start being issued out of order, the whole thing just becomes an embarrassing wart. It was a great trick for exactly one CPU design, and never belonged in an ISA.