4 ms·
Interesting idea, but with some drawbacks. 1) No JTAG interface. 2) No SEU mitigations. 3) Power consumption likely at least two orders of magnitude higher. 4)
by anonymousiam 6y ago
Interesting idea, but with some drawbacks.
1) No JTAG interface.
2) No SEU mitigations.
3) Power consumption likely at least two orders of magnitude higher.
4) Higher cost.
Some potential benefits:
1) Runs faster.
2) Reduced part count.
3) Easy integration with other FPGA elements.
I will add that the GNU tool chain for the MSP-430 is horrible. TI has a much better C compiler which they previously charged $100 for, but it's been free for the last four years.
- deleted 6y ago[deleted]
- throwaway81523 6y agoIdea is to have a fairly simple synthesizeable softcore with an existing toolchain of some sort. SEU mitigation seems like it belongs at a lower abstraction level, the FPGA fabric itself. I'd like to hope RiscV hard macros start showing up on low end FPGA's soon, just like we have DSP and RAM blocks, so we can stop chewing up LUTs with softcores. ARM cores are on high end FPGAs now and the ARM tax must account for part of that differentiation. RiscV bypasses the tax.