5 ms·
The MIPS R4000, part 9: Stupid branch delay slot tricks (2018)
- garaetjjte 6y agoWhy Microsoft must always horribly break all pages during every CMS migration? All links to MSDN blogs on this page are broken. For one of the links they even managed to mangle the link itself, so good luck finding it on web archive. Comments are gone too. And it's not even limited to blogs, clicking some link in Microsoft docs and getting redirected to main page happens frequently too...
- userbinator 6y agoI see it as a sign of the "quantity over quality" trend that has affected the software industry in general. The MSDN->docs.microsoft.com migration was a horrible regression: https://news.ycombinator.com/item?id=11626886 https://news.ycombinator.com/item?id=11626886 I've ranted about its decline a few times on here before, notably this huge fuckup that still remains a year after my original comment (and I noticed it several years back before that --- when they first started destroying MSDN): https://news.ycombinator.com/item?id=21832963 https://news.ycombinator.com/item?id=21832963
- toast0 6y agoMicrosoft doesn't understand the Internet and never has.
- ncmncm 6y agoTo me it demonstrates that users of Microsoft products are not considered the customer. Developers are not the customer. I have not discovered anybody who is the customer. There might not be one. That is typically a characteristic of a monopoly. ("We don't have to care, we're the phone company!") At Apple, Steve was the one and only customer. Buyers were invited to bask in his glory, for a price. Now, is there one?
- yellowapple 6y agoSometimes I wonder what the world would be like if the other Steve was Apple's one and only customer.
- jiggawatts 6y agoOr how on TechNet all comments are duplicated? Or how on TechNet all comments are duplicated?
- pronoiac 6y agoHere's the Wayback Machine archive for the original MSDN location, with comments and somewhat more functional links: https://web.archive.org/web/20180418231114/https://blogs.msdn.microsoft.com/oldnewthing/20180412-00/?p=98495 https://web.archive.org/web/20180418231114/https://blogs.msd...
- rmrfchik 6y agoBroken links are in heart of Microsoft. Open Event Browser on Windows 10, choose System and click in random message. Click link which lead to support.microsoft.com with detailed message explanation. Should lead. Except it doesn't. Never heard Windows 10 has reached EoL. Neither Event Viewer. Neither "System" component from Windows 10.
- marcodiego 6y agoAFAIK nt was to be portable from the beginning. Never was too popular beyond x86. I had the opportunity of playing with SGI Fuel and O2, both with MIPS processors, in early 2000's and they were severely limited by having only one viable OS. Linux on these never got all the drivers it needed. Even today such machines would be useful if documentation about its hardware was made available.
- eschaton 6y agoStrange, my Octane, O2, and Indigo2 don’t really feel limited by running the operating system that was developed specifically for them.
- marcodiego 6y agoIt was soon impossible to install software except by those "that was developed specifically for them". Even compiling new qt versions, which made the Fuel become very hot, was troublesome to build more modern software.
- speed_spread 6y agoAlthough not too bad a Unix, IRIX was pretty much a closed environment. Support from most open source libraries and apps was poor. I remember running Netscape on my Indy and... that was it. It was a pay-to-play environment, never intended to be put in the hands of enthusiasts. Even the C compiler was extra you had to pay for. By comparison, Sun workstations were _way_ more open than SGI's.
- bigbillheck 6y agoA few years ago I was programming for a VLIW processor that had delay slots for all kinds of instructions. These were longer, however; I think the branch instructions had a delay of about 5 so you could pack all sorts of mischief in there.
- ajross 6y agoInstruction scheduling rules in VLIW are for a slightly different reason than the MIPS BDS. VLIW is designed to expose the parallel instruction dispatch capabilities to the compiler in a way that doesn't require hardware to track dependencies between them. Fundamentally you're tracking register/data dependencies, though often there is a latency minimum the compiler is expected to enforce. But the rules there are present for correctness, not performance per se. With MIPS, the problem being solved that the original 4-stage pipeline always had exactly one cycle of latency between the evaluation of a branch decision and the fetch of the next instruction. So by always executing the next instruction unconditionally they could sneak in exactly one extra instruction per branch. It was a 100% pure performance play, and actually fairly clever at the time. MIPS was frighteningly fast when it was released in ~1987, and this was one of the reasons why. ...until the second CPU. Once that pipeline gets longer, the branch prediction logic gets deeper, or instructions start being issued out of order, the whole thing just becomes an embarrassing wart. It was a great trick for exactly one CPU design, and never belonged in an ISA.
- nayuki 6y agoBlog post is dated 2018-04-12; this needs to be in the title.
- deleted 6y ago[deleted]