> Anyone know how this affects power, compute, or communications metrics compared to monolithic designs? It does effect ennormously, but everything is highly d

> Anyone know how this affects power, compute, or communications metrics compared to monolithic designs? It does effect ennormously, but everything is highly design specific. The die size limits are not only yield related. Power, and clock have stopped scaling few generations ago. New chips have more, and more disaggregated, independent blocks separated by asynchronous interfaces to accomodate more clock, and power domains. If you have to break a chip along such domain boundary, you loose little in terms of speed unlike if you did it right across registers, logic, and synchronous parallel links. Caches also stopped scaling too, and making them bigger, also makes them slower. Instead, more elaborate application specific cache hierarchies are getting popular. L1-2 get smaller, and faster, but L3 can be made to ones fantasy: eDRAM, standalone SRAM, stacked memory etc.