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Manufacturing the chip-lets independently appears to be an interesting approach to maximizing yields. If anyone component has a defect, you just assemble using

Manufacturing the chip-lets independently appears to be an interesting approach to maximizing yields. If anyone component has a defect, you just assemble using a different chip-let, as opposed to it affecting the final product. Anyone know how this affects power, compute, or communications metrics compared to monolithic designs? Or am I off in thinking this approach maximizes yields?

zamadatix 6y ago
See/compare AMD's CPUs from the last couple of years to Intel's - they use the chiplet approach with up to 8+1 in their Epyc CPUs for example.
baybal2 6y ago
> Anyone know how this affects power, compute, or communications metrics compared to monolithic designs? It does effect ennormously, but everything is highly design specific. The die size limits are not only yield related. Power, and clock have stopped scaling few generations ago. New chips have more, and more disaggregated, independent blocks separated by asynchronous interfaces to accomodate more clock, and power domains. If you have to break a chip along such domain boundary, you loose little in terms of speed unlike if you did it right across registers, logic, and synchronous parallel links. Caches also stopped scaling too, and making them bigger, also makes them slower. Instead, more elaborate application specific cache hierarchies are getting popular. L1-2 get smaller, and faster, but L3 can be made to ones fantasy: eDRAM, standalone SRAM, stacked memory etc.
ksec 6y ago
This ( EMIB ) is suppose to be the most interesting part of the announcement but most of the discussion seems to focused on CUDA / One-API. >Or am I off in thinking this approach maximizes yields? This is absolutely the case here especially for HPC or high performance market where they are all previously served by large die size solutions. You can also use the best node for each tiles / chipsets. Example I/O die may use other node for lower power consumption while Compute die uses High power node to push performance. High Density node for SRAM, low cost node for simple function accelerator etc. You can now customise each part of the tiles/chiplet best according to your target power/performance/cost equation. Now of course their are trade offs, Intel Tiles packaging (EMIB, Embedded Multi-die Interconnect Bridge) is expensive. And it adds tiny latency for not being on die. Although you could argue you saved latency for certain parts with it not being off a PCIE bus. But this is very exciting. The best part is with this announcement that you can use Tiles and Chiplet from other foundries on Intel packaging! You could theoretically use Global Foundry ( or Samsung ) FD-SOI node for certain applications and still be on the same packaging. You can now truly mix and match to the maximum. Not so good part is we are still limited by TDP design. And I dont see anything being done in the consumer / prosumer space.

zamadatix 6y ago

See/compare AMD's CPUs from the last couple of years to Intel's - they use the chiplet approach with up to 8+1 in their Epyc CPUs for example.

baybal2 6y ago

> Anyone know how this affects power, compute, or communications metrics compared to monolithic designs? It does effect ennormously, but everything is highly design specific. The die size limits are not only yield related. Power, and clock have stopped scaling few generations ago. New chips have more, and more disaggregated, independent blocks separated by asynchronous interfaces to accomodate more clock, and power domains. If you have to break a chip along such domain boundary, you loose little in terms of speed unlike if you did it right across registers, logic, and synchronous parallel links. Caches also stopped scaling too, and making them bigger, also makes them slower. Instead, more elaborate application specific cache hierarchies are getting popular. L1-2 get smaller, and faster, but L3 can be made to ones fantasy: eDRAM, standalone SRAM, stacked memory etc.

ksec 6y ago

This ( EMIB ) is suppose to be the most interesting part of the announcement but most of the discussion seems to focused on CUDA / One-API. >Or am I off in thinking this approach maximizes yields? This is absolutely the case here especially for HPC or high performance market where they are all previously served by large die size solutions. You can also use the best node for each tiles / chipsets. Example I/O die may use other node for lower power consumption while Compute die uses High power node to push performance. High Density node for SRAM, low cost node for simple function accelerator etc. You can now customise each part of the tiles/chiplet best according to your target power/performance/cost equation. Now of course their are trade offs, Intel Tiles packaging (EMIB, Embedded Multi-die Interconnect Bridge) is expensive. And it adds tiny latency for not being on die. Although you could argue you saved latency for certain parts with it not being off a PCIE bus. But this is very exciting. The best part is with this announcement that you can use Tiles and Chiplet from other foundries on Intel packaging! You could theoretically use Global Foundry ( or Samsung ) FD-SOI node for certain applications and still be on the same packaging. You can now truly mix and match to the maximum. Not so good part is we are still limited by TDP design. And I dont see anything being done in the consumer / prosumer space.