3 ms·

The NEO430 Processor

42 points by kqr2 6y ago

mkesper 6y ago
TFA: This project is still active but is currently shelved as I am focusing on the NEO430's "big brother": The RISC-V-powered 32-bit NEORV32 https://github.com/stnolting/neorv32 https://github.com/stnolting/neorv32.
- elromulous 6y ago
  I was about to post with "how is this different from the various other vhdl / verilog risc v implementations", but saw the incredibly detailed datasheet. That alone is very impressive.
anonymousiam 6y ago
Interesting idea, but with some drawbacks. 1) No JTAG interface. 2) No SEU mitigations. 3) Power consumption likely at least two orders of magnitude higher. 4) Higher cost. Some potential benefits: 1) Runs faster. 2) Reduced part count. 3) Easy integration with other FPGA elements. I will add that the GNU tool chain for the MSP-430 is horrible. TI has a much better C compiler which they previously charged $100 for, but it's been free for the last four years.
- deleted 6y ago
  [deleted]
- throwaway81523 6y ago
  Idea is to have a fairly simple synthesizeable softcore with an existing toolchain of some sort. SEU mitigation seems like it belongs at a lower abstraction level, the FPGA fabric itself. I'd like to hope RiscV hard macros start showing up on low end FPGA's soon, just like we have DSP and RAM blocks, so we can stop chewing up LUTs with softcores. ARM cores are on high end FPGAs now and the ARM tax must account for part of that differentiation. RiscV bypasses the tax.
stefan_ 6y ago
Interesting that you can implement a TRNG in FPGA synthesized logic. It seems to be sampling the output of the inverter chain not necessarily the jitter? I guess the two are related.
- mkj 6y ago
  You might be interested in https://github.com/betrusted-io/betrusted-wiki/wiki/TRNG-characterization#ring-oscillator https://github.com/betrusted-io/betrusted-wiki/wiki/TRNG-cha...
rijoja 6y ago
The MSP430 is running in a ridiculously small power envelope is it not? Obviously this wouldn't be the case while running it on a FPGA. Are there other chips that are more power-efficient for similar capabilities that are popular?

42 points by kqr2 6y ago

TFA: This project is still active but is currently shelved as I am focusing on the NEO430's "big brother": The RISC-V-powered 32-bit NEORV32 https://github.com/stnolting/neorv32 https://github.com/stnolting/neorv32.

elromulous 6y ago
I was about to post with "how is this different from the various other vhdl / verilog risc v implementations", but saw the incredibly detailed datasheet. That alone is very impressive.

anonymousiam 6y ago

Interesting idea, but with some drawbacks. 1) No JTAG interface. 2) No SEU mitigations. 3) Power consumption likely at least two orders of magnitude higher. 4) Higher cost. Some potential benefits: 1) Runs faster. 2) Reduced part count. 3) Easy integration with other FPGA elements. I will add that the GNU tool chain for the MSP-430 is horrible. TI has a much better C compiler which they previously charged $100 for, but it's been free for the last four years.

deleted 6y ago
[deleted]
throwaway81523 6y ago
Idea is to have a fairly simple synthesizeable softcore with an existing toolchain of some sort. SEU mitigation seems like it belongs at a lower abstraction level, the FPGA fabric itself. I'd like to hope RiscV hard macros start showing up on low end FPGA's soon, just like we have DSP and RAM blocks, so we can stop chewing up LUTs with softcores. ARM cores are on high end FPGAs now and the ARM tax must account for part of that differentiation. RiscV bypasses the tax.

stefan_ 6y ago

Interesting that you can implement a TRNG in FPGA synthesized logic. It seems to be sampling the output of the inverter chain not necessarily the jitter? I guess the two are related.

mkj 6y ago
You might be interested in https://github.com/betrusted-io/betrusted-wiki/wiki/TRNG-characterization#ring-oscillator https://github.com/betrusted-io/betrusted-wiki/wiki/TRNG-cha...

rijoja 6y ago

The MSP430 is running in a ridiculously small power envelope is it not? Obviously this wouldn't be the case while running it on a FPGA. Are there other chips that are more power-efficient for similar capabilities that are popular?