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They don't. A few other ARM CPUs implement TSO already (by default, due to their design), it's just not an architectural/standard feature that software can rely
by marcan_42 6y ago
They don't. A few other ARM CPUs implement TSO already (by default, due to their design), it's just not an architectural/standard feature that software can rely on.
- monocasa 6y agoRight, other cores implement TSO by (because a stupid simple core will be TSO sort of by default), but it's a pretty unique thing to have a runtime TSO switch. And it'd be incredibly stupid of them not to have a patent on it unless there's some clear prior art for exactly their implementation since we're in a first to file system in the US. Otherwise they're asking for someone else to patent it and troll them for an easy cash grab.
- anarazel 6y agoSparc v9 had registers to change the consistency model. 1993. See "5.2.1.4 PSTATE_mem_model (MM)" in https://cr.yp.to/2005-590/sparcv9.pdf https://cr.yp.to/2005-590/sparcv9.pdf
- monocasa 6y agoFair enough. That's what I get for talking in absolute terms.
- saagarjha 6y agoNvidia’s Carmel is sequentially consistent.
- monocasa 6y agoMy whole point as been around _selectable_ consistency, which is a rarity. Yes, there are many cores with stricter than necessary consistency, but very very very few allow you to switch consistency models at runtime. Hence my original statement about the "cute _optional_ TSO memory model".