> I imagine it might have a significant performance impact, It depends on the CPU: MIPS has(had if you consider MIPS dead) some integer operations which trappe

> I imagine it might have a significant performance impact, It depends on the CPU: MIPS has(had if you consider MIPS dead) some integer operations which trapped in case of integer overflow AFAIK the 'trapping operations' were as fast as the non-trapping operations (when no overflow occurred of course). Unfortunately even though RISC-V is MIPS successor, it doesn't have those trapping operations :-( I must admit I don't understand why no modern CPU ISA has these trapping instructions: explicit checks have an 'instruction cache cost', so users won't enable them which reduces security..