3 ms·
Very interesting. Any sense of how many transistors / gates would be a likely minimum needed for an RISC-V implementation like this?
by klelatti 6y ago
Very interesting. Any sense of how many transistors / gates would be a likely minimum needed for an RISC-V implementation like this?
- retrac 6y agoMy last rough sketch came out to about 400 gates, excluding the flip-flops. If one cuts even more corners, that number could come down much further. For example, an adder isn't actually necessary and can be replaced with lookup tables and bit-twiddling, again at the cost of cycles and more microcode. See https://hackaday.io/project/161251-1-square-inch-ttl-cpu https://hackaday.io/project/161251-1-square-inch-ttl-cpu -- while not RISC-V it demonstrates some of these principles in action, taken to the extreme. That design consists of: one 4 bit counter, four 8-bit flip-flops, one quad OR gate, one dual 2-to-4 demux, and one 128 KB Flash ROM. Including the flip-flops (and obviously excluding the Flash memory) that comes out to about 200 or so gates by my count, and the microcode/emulation program implements a fairly typical CISC 16 bit processor. It's not even all that inefficient, with under 100 cycles per instruction on average.
- klelatti 6y agoThanks. As you say having LLVM be able to target a CPU built with so few gates is pretty remarkable!