46 ms·
Along the same lines of minimizing the amount of logic used at the cost of cycles, there's SERV which uses a bit-serial implementation with a 1-bit data path: h
by retrac 6y ago
Along the same lines of minimizing the amount of logic used at the cost of cycles, there's SERV which uses a bit-serial implementation with a 1-bit data path: https://github.com/olofk/serv https://github.com/olofk/serv
From time to time, I have been tempted to design a RISC-V implementation out of discrete 74xx components. Sure, there are plenty of projects out there to build your own processor from scratch like that, but most of them aren't LLVM targets!
The 32-bit datapaths and need for so many registers makes it a bit daunting to approach directly. That approach would probably end up similar in scale to a MIPS implementation I once saw done like that. (Can't find the link, but it was about half a dozen A4-sized PCBs).
Retreating to an 8-bit microcoded approach and lifting all the registers and complexity into RAM and software is a very attractive idea. Might even fit on a single Eurocard. It's not like a discrete TTL RISC-V implementation would ever be a speed demon, either way.
- klelatti 6y agoVery interesting. Any sense of how many transistors / gates would be a likely minimum needed for an RISC-V implementation like this?
- retrac 6y agoMy last rough sketch came out to about 400 gates, excluding the flip-flops. If one cuts even more corners, that number could come down much further. For example, an adder isn't actually necessary and can be replaced with lookup tables and bit-twiddling, again at the cost of cycles and more microcode. See https://hackaday.io/project/161251-1-square-inch-ttl-cpu https://hackaday.io/project/161251-1-square-inch-ttl-cpu -- while not RISC-V it demonstrates some of these principles in action, taken to the extreme. That design consists of: one 4 bit counter, four 8-bit flip-flops, one quad OR gate, one dual 2-to-4 demux, and one 128 KB Flash ROM. Including the flip-flops (and obviously excluding the Flash memory) that comes out to about 200 or so gates by my count, and the microcode/emulation program implements a fairly typical CISC 16 bit processor. It's not even all that inefficient, with under 100 cycles per instruction on average.
- klelatti 6y agoThanks. As you say having LLVM be able to target a CPU built with so few gates is pretty remarkable!
- monocasa 6y agoIf you don't know of it already, you might like the book Bit-Slice Microprocessor Design written by Mick and Brick. It's written to be very AM2900 specific, but a lot of the techniques would apply to microcoded TTL processors with just a little more work on your end. And it really does a good job of exploring the space of microcoded minicomputer design in an interesting way.
- retrac 6y agoOoh. I had not seen that one. Thanks!