Oh for sure. Even if it’s the P6’s microcode (the first with updatable code), I’d take it. I’ve always wondered what microcode looks like in these processors, a

Oh for sure. Even if it’s the P6’s microcode (the first with updatable code), I’d take it. I’ve always wondered what microcode looks like in these processors, and how it functions. There is “p6tools”[0][1] which looks interesting. But if Intel released info on it, that’d be really cool. Sidenote: Ken Shirriff has reverse engineered the ARM1’s microcode,[2] but it’s a “horizontal” microcode (bits control CPU blocks directly) while x86 uses “vertical” (RISC-like) microcode. [0]: https://github.com/peterbjornx/p6tools https://github.com/peterbjornx/p6tools [1]: https://www.youtube.com/watch?v=4oFOpDflJMA https://www.youtube.com/watch?v=4oFOpDflJMA (slides: https://hardwear.io/netherlands-2020/presentation/under-the-hood-of-a-CPU-hardwear-io-nl-2020.pdf https://hardwear.io/netherlands-2020/presentation/under-the-...) [2]: http://www.righto.com/2016/02/reverse-engineering-arm1-processors.html http://www.righto.com/2016/02/reverse-engineering-arm1-proce...