6 ms·
The instruction in question looks to be encoded as 0f 0a. Which, sure enough, is missing from the official reference - https://files.catbox.moe/ktzqfg.png http
by moonchild 6y ago
The instruction in question looks to be encoded as 0f 0a. Which, sure enough, is missing from the official reference - https://files.catbox.moe/ktzqfg.png https://files.catbox.moe/ktzqfg.png
- userbinator 6y agoAccording to https://www.geoffchappell.com/notes/windows/archive/linkcpu.htm https://www.geoffchappell.com/notes/windows/archive/linkcpu.... this was at one point a proposed cache flush instruction (as the mnemonic suggests). More detailed information here: https://www.os2museum.com/wp/curious-instructions/ https://www.os2museum.com/wp/curious-instructions/
- _kbh_ 6y agothe other appears to 0f 0e. at least if you go off this tweet. https://twitter.com/eigma/status/1373155650432290819 https://twitter.com/eigma/status/1373155650432290819 . 0f 0e is a 3DNow! instruction that AMD supported but not intel, which would explain why it has a mnemonic in Ghidra even though its undocumented for Intel processors.
- moonchild 6y agoInteresting. Not sure how trustworthy that account is. The only 2-byte sequence documented by amd and not by intel that starts with 0f is, in fact, 0f 0e; that is FEMMS, which does match up with the length of the obscuring bar in the first reply. And it does seem plausible that intel would pick proximal instructions for 'read' and 'write' of uarch state.
- _kbh_ 6y agoOnly reason I consider it trust worthy is that it was retweeted by Mark Ermolov, which makes me think they got it right.