3 ms·
I don't quite get this. Vivado uses Verilog as input. nMigen (and similar tools such as Chisel and SpinalHDL) just write the Verilog for you. You still use Viva
by brucehoult 6y ago
I don't quite get this. Vivado uses Verilog as input. nMigen (and similar tools such as Chisel and SpinalHDL) just write the Verilog for you. You still use Vivado to generate the actual bitstream (assuming you're using an Xilinx FPGA).
- 127 6y agoFrom zero to Microblaze inside PetaLinux is a couple of minutes of work (and some waiting around for it to compile) and has plenty of tutorials. nMigen SoC has a Github repo that is "TBD". Maybe I just didn't look deep enough?