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Cool stuff. Well presented. Just by coincidence was just reading this yesterday: https://vivonomicon.com/2020/06/13/lets-write-a-minimal-risc-v-cpu-in-nmigen/ h
by 127 6y ago
Cool stuff. Well presented. Just by coincidence was just reading this yesterday: https://vivonomicon.com/2020/06/13/lets-write-a-minimal-risc-v-cpu-in-nmigen/ https://vivonomicon.com/2020/06/13/lets-write-a-minimal-risc...
nMigen is super interesting but I'm still stuck in Xilinx Vivado as a beginner because it makes integrating small cores so easy. Full RISC-V SoC that does something useful in the FPGA part and runs a small version of Linux and programs that call the FPGA part would be super neat.
Seems small RISCV cores can be written very quickly https://github.com/darklife/darkriscv#introduction https://github.com/darklife/darkriscv#introduction, but actually making them production hardware take a long time: https://zipcpu.com/zipcpu/2021/03/18/zipos.html https://zipcpu.com/zipcpu/2021/03/18/zipos.html
- brucehoult 6y agoI don't quite get this. Vivado uses Verilog as input. nMigen (and similar tools such as Chisel and SpinalHDL) just write the Verilog for you. You still use Vivado to generate the actual bitstream (assuming you're using an Xilinx FPGA).
- 127 6y agoFrom zero to Microblaze inside PetaLinux is a couple of minutes of work (and some waiting around for it to compile) and has plenty of tutorials. nMigen SoC has a Github repo that is "TBD". Maybe I just didn't look deep enough?