3 ms·
interesting. if i'm reading the wikipedia article about this right, they were essentially SoCs with on-die high speed networking and no shared ram? the ring arc
by a-dub 6y ago
interesting. if i'm reading the wikipedia article about this right, they were essentially SoCs with on-die high speed networking and no shared ram? the ring architecture reminds me a bit of multicore x86...
- __d 6y agoThat's about right, yes. There were 4 x 20Mbps links and you could use them to directly connect to other CPUs (so, a mesh or torus) or to a fabric. The link protocol was very simple. Each CPU had local DRAM, but there usually wasn't much: 1-16MB was typical. Unlike most CPUs, there weren't really registers as such: you had a high-speed stack instead (on die). So an add instruction would pop the top two stack locations, and push the sum.