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For many things I would take HLS over writing SystemVerilog. My background is software, but I've written a modest amount SystemVerilog professionally in recent
by jsolson 6y ago
For many things I would take HLS over writing SystemVerilog. My background is software, but I've written a modest amount SystemVerilog professionally in recent years. While there are specific cases where I'd still pick SystemVerilog (building an AXI peripheral with a specific address space layout or unique semantics for that address space), I'd tend to prefer HLS for anything actually dealing with complex data processing. Think packet pipelines, sorts, database joins, index processing, etc. If you were already in the mindset of thinking about streaming data through a pipeline (as you might in SystemVerilog) you can write fairly boring looking C++ with ordinary unit tests and the HLS tooling will do a reasonable job of turning it into equivalent pipelined Verilog.
- randrews9 6y agoTotally agree. Certain signal processing pipelines that FPGAs are often targeted at map very well to HLS, often with 10x or more code reduction. Production SoCs sometimes use similar tech for less power/performance critical blocks. Mentor graphics catapult HLS marketing material contains some note that NVENC on the maxwell generation of Nvidia GPUS was coded in HLS.