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I don't think so either. One thing that's interesting here is that this ties into LLVM - perhaps other LLVM languages like Julia or Rust could interop?
by UncleOxidant 6y ago
I don't think so either. One thing that's interesting here is that this ties into LLVM - perhaps other LLVM languages like Julia or Rust could interop?
- ancharm 6y agoI've kind of always felt that synthesizable Verilog/SystemVerilog was good, but the verification side was just too complex and had too much bloat. Testing hardware with Python (like Cocotb) feels more on the right track as a high level UI. But easily pluggable APIs for foreign SW languages are key as well. Hardware software co-design is only becoming more important.