3 ms·

> In 2010 MIPS wanted $2 million from Berkeley to allow them to use the MIPS instruction encodings Do you have a source for that? I see that you're a RISC-V ex

> In 2010 MIPS wanted $2 million from Berkeley to allow them to use the MIPS instruction encodings Do you have a source for that? I see that you're a RISC-V expert, and I know MIPS, Inc. is notorious for patent lawsuits, so I trust you. I'm just curious about the Berkeley project.

KirillPanov 6y ago
Patterson always smirks when people ask him what the "V" is for, and mumbles an uncharacteristically vague reply (something about it being the fifth chip project he's worked on or something like that...) It's no coincidence that MIPS used roman numerals for its architectures, MIPS-I, MIPS-II, MIPS-III, MIPS-IV, and MIPS-V. So instead of using MIPS-V Berkeley created RISC-V. You aren't going to get anybody who was involved to say this on the record -- that they changed just barely enough to evade the licensing (instruction encoding) and trademark ("MIPS-V") problems. Openly admitting in print that it was a "minimum noninfringing change" simply invites lawsuits claiming that they were one hair's width on the wrong side of that line.
- indolering 6y ago
  I think you understate the level of IP vetting RISC-V has undergone. All but 6 instructions in the RV32G instruction set could be found in implementations that were at least 20 years old; the remaining six were novel [1]. RISC-V owes MIPS about as much as MIPS owes Patterson. MIPS-V was already ~15 years old when RISC-V was first used in the classroom. RISC-V purposefully paired back the layers of marketing cruft and failed experiments that had grown over Patterson et al.'s original RISC architecture. There is less confidence in the extensions, but as RISC-V turns 10 ... patent trolls had better hurry if they want to extort anyone based on the ISA alone. [1]: https://live-risc-v.pantheonsite.io/wp-content/uploads/2016/02/EECS-2016-6.pdf https://live-risc-v.pantheonsite.io/wp-content/uploads/2016/...
  - brucehoult 6y ago
    Part of joining RISC-V International is signing a document irrevocably certifying that RISC-V doesn't infringe any of your patents, so that door is definitely closed for MIPS now anyway. It is a little weird that there is an actual preference in proposing instructions for RISC-V extensions to demonstrate that the instruction was patented but the patent has expired, or at least that the instruction was publicly documented in some ISA at least a couple of decades ago. By and large, RISC-V is not trying to be novel, but to bring together and simplify established best practice. I did invent what is believed to be an entirely novel instruction for the RISC-V B extension: GORC. The other instruction GORC shares circuitry with, GREV, is also believed to not have been implemented in an ISA before, though it has been proposed in the literature.
- brucehoult 6y ago
  Well no that's not right. There have been "minimum noninfringing change" MIPS clones, by doing something like leaving out the patented unaligned load and store instructions, but otherwise being identical and compatible with MIPS software and compilers etc. RISC-V is completely different and incompatible with MIPS at the binary level. The opcodes are all different. The opcode and register fields are build from opposite ends of the word. The conditional branching model is different (MIPS r6 later copied RISC-V's version). The sizes of immediate and offset values is only 12 bits vs 16 in MIPS – which is a major reason for RISC-V having a lot more encoding space free for future instructions. There are of course no branch or load delay slots in RISC-V – something that MIPS again copied in r6. There is a certain flavour that is similar, but the details are utterly different.
brucehoult 6y ago
Krste (or maybe Dave?) said so in a video somewhere not that long ago -- I assume in the RISC-V International channel on youtube but I don't recall which one.
- segfaultbuserr 6y ago
  Thanks.

KirillPanov 6y ago

Patterson always smirks when people ask him what the "V" is for, and mumbles an uncharacteristically vague reply (something about it being the fifth chip project he's worked on or something like that...) It's no coincidence that MIPS used roman numerals for its architectures, MIPS-I, MIPS-II, MIPS-III, MIPS-IV, and MIPS-V. So instead of using MIPS-V Berkeley created RISC-V. You aren't going to get anybody who was involved to say this on the record -- that they changed just barely enough to evade the licensing (instruction encoding) and trademark ("MIPS-V") problems. Openly admitting in print that it was a "minimum noninfringing change" simply invites lawsuits claiming that they were one hair's width on the wrong side of that line.

indolering 6y ago
I think you understate the level of IP vetting RISC-V has undergone. All but 6 instructions in the RV32G instruction set could be found in implementations that were at least 20 years old; the remaining six were novel [1]. RISC-V owes MIPS about as much as MIPS owes Patterson. MIPS-V was already ~15 years old when RISC-V was first used in the classroom. RISC-V purposefully paired back the layers of marketing cruft and failed experiments that had grown over Patterson et al.'s original RISC architecture. There is less confidence in the extensions, but as RISC-V turns 10 ... patent trolls had better hurry if they want to extort anyone based on the ISA alone. [1]: https://live-risc-v.pantheonsite.io/wp-content/uploads/2016/02/EECS-2016-6.pdf https://live-risc-v.pantheonsite.io/wp-content/uploads/2016/...
- brucehoult 6y ago
  Part of joining RISC-V International is signing a document irrevocably certifying that RISC-V doesn't infringe any of your patents, so that door is definitely closed for MIPS now anyway. It is a little weird that there is an actual preference in proposing instructions for RISC-V extensions to demonstrate that the instruction was patented but the patent has expired, or at least that the instruction was publicly documented in some ISA at least a couple of decades ago. By and large, RISC-V is not trying to be novel, but to bring together and simplify established best practice. I did invent what is believed to be an entirely novel instruction for the RISC-V B extension: GORC. The other instruction GORC shares circuitry with, GREV, is also believed to not have been implemented in an ISA before, though it has been proposed in the literature.
brucehoult 6y ago
Well no that's not right. There have been "minimum noninfringing change" MIPS clones, by doing something like leaving out the patented unaligned load and store instructions, but otherwise being identical and compatible with MIPS software and compilers etc. RISC-V is completely different and incompatible with MIPS at the binary level. The opcodes are all different. The opcode and register fields are build from opposite ends of the word. The conditional branching model is different (MIPS r6 later copied RISC-V's version). The sizes of immediate and offset values is only 12 bits vs 16 in MIPS – which is a major reason for RISC-V having a lot more encoding space free for future instructions. There are of course no branch or load delay slots in RISC-V – something that MIPS again copied in r6. There is a certain flavour that is similar, but the details are utterly different.

brucehoult 6y ago

Krste (or maybe Dave?) said so in a video somewhere not that long ago -- I assume in the RISC-V International channel on youtube but I don't recall which one.

segfaultbuserr 6y ago
Thanks.