11 ms·

This is huge. It looks like the only architectures widely-deployed in ten years will be x86, ARM, Power, and RISC-V (maybe also SPARC64 in Japan, although that'

This is huge. It looks like the only architectures widely-deployed in ten years will be x86, ARM, Power, and RISC-V (maybe also SPARC64 in Japan, although that's rare in the US).

tyingq 6y ago
The "not ARM based" MCU market might be interesting to watch as well. Not just for RISC-V, but also as ARM MCUs continue to drop in power needs and unit cost.
dragontamer 6y ago
The big innovation in architectures is in the SIMD world. AVX512 (x86 512-bit), SVE (ARM 512-bit), NVidia PTX / SASS (32x32-bit), AMD RDNA (32x32-bit), AMD CDNA (64x32-bit). 64-bit cores (aka: classic CPUs) are looking like a solved problem, and are becoming a commodity. SIMD compute however, remains an open question. NVidia probably leads today, but there seems to be plenty of room for smaller players. Heck, one major company (AMD) is pushing 32x32-bit on one market (6xxx series) and 64x32-bit in another market (MI100 / Supercomputers).
- tyingq 6y ago
  Fujitsu seems like a leader for SIMD via their A64FX. I wonder if they will ever venture outside of the supercomputing niche.
  - dragontamer 6y ago
    SVE is looking like a general-purpose ARM instruction set in the future. I believe the Neoverse V-cores (high-performance) will have access to the SVE instructions for example. So the SVE-SIMD is not necessarily locked to Fujitsu (though Fujitsu's particular implementation is probably crazy good. HBM2 + 512-bit wide and #1 supercomputer in the world and all...)
- londons_explore 6y ago
  SIMD today is only really helpful with a few usecases. If you want to encode some video, decode some jpegs, or do a physics simulation quicker, it's really going to help. It won't boot Linux any quicker tho. I suspect for consumer uses, SIMD is already used for nearly all the use cases it can be.
  - dragontamer 6y ago
    Are you sure about that? The original SIMD-papers in the 1980s show how to compile a Regex into a highly-parallel state machine and then "reduced" (aka: Scan / Prefix-operation: https://en.wikipedia.org/wiki/Prefix_sum https://en.wikipedia.org/wiki/Prefix_sum). A huge amount of operations, such as XML-whitespace removal (aka: SIMD Steam Compacting), Regular Expressions, and more, have been proven ~30 to 40 years ago to benefit from SIMD compute. Yet such libraries don't exist today yet. SIMD compute is highly niche, and clearly today's population is overly focused on deep-learning... without even seeing the easy opportunities of XML parsing or simple regex yet. Further: additional opportunities are being discovered in O(n^2) operations: such as inner-join operations on your typical database. Citations. * For Regular Expressions: Read the 1986 paper "DATA PARALLEL ALGORITHMS". Its an easy read. Hillis / Steele are great writers. They even have the "impossible Linked List" parallelism figured out in there (granted: the nodes are located in such a way that the SIMD-computer can work with the nodes. But... if you had a memory-allocator that worked with their linked-list format, you could very well implement their pointer-jumping approach to SIMD-linked list traversal) * For whitespace folding / removal, see http://www.cse.chalmers.se/~uffe/streamcompaction.pdf http://www.cse.chalmers.se/~uffe/streamcompaction.pdf. They don't cite it as XML-whitespace removal, but it seems pretty obvious to me that it could be used for parallel whitespace removal in O(lg(n)) steps. * Database SIMD: http://www.cs.columbia.edu/~kar/pubsk/simd.pdf http://www.cs.columbia.edu/~kar/pubsk/simd.pdf . Various operations have been proven to be better on SIMD, including "mass binary search" (one binary search cannot be parallelized. But if you have 5000-binary searches operating in parallel, its HIGHLY efficient to execute all 5000 in a weird parallel manner, far faster than you might originally imagine). ---------- SIMD-cuckoo hashing, SIMD-skip lists, etc. etc. There's so many data-structures that haven't really been fleshed out on SIMD yet outside of research settings. They have been proven easy to implement and simple / clean to understand. They're just not widely known yet.
- gnufx 6y ago
  The V in SVE is for vector, the S isn't for SIMD, and it's length-agnostic; I don't know how similar it is to the RISC-V vector extension. Think CDC, Cray, NEC, not AMD/Intel. I guess the recent innovation in that space is actual matrix multiplication instructions in CPUs.
  - dragontamer 6y ago
    Some GPU assembly advancements... * Bpermute and permute. (Pshufb is like permute, a gather operation. Bpermute is the opposite, like a scatter. Bpermute Doesn't exist on x86 yet) * __shared__ memory crossbar: every simd unit can read, or write, to shared memory in parallel per clocktick. The crossbar can also broadcast 1-to-all each clocktick. * Butterfly permute: the fundamental pattern in permutations for a variety of operations. Most noticably for scan, and FFTs. Butterfly networks are closely related to pext and pdep implementation (showing how common that particular permute is). * 8+ way hyperthreads / SMT. GPUs have very bad latency, but very high SMT counteracts that problem well in practice. * PCIe Atomics: perform those compare and swap negotiations over I/O, allowing tight CPU and GPU memory integration. * Crazy RAM. 1000GBps on HBM2. 800GBps over GDDR6x thanks to 2-bits transferred per clock ticks. * Crazy networks. AMD Infinity fabric pushes over 100GB. NVlink is 600GBps. A GPU network link has more bandwidth than a typical CPU's DDR4 RAM bandwidth. * NVidia SASS has the craziest instruction set, the compiler figures out read / write hazards and publishes them in the SASS assembly itself. NVidias ISA decoder + assembler team is doing something crazy here, the likes I haven't seen in any other instruction set ever. * "Ballot" instructions. Its... really hard to explain why these are useful. They just are, lol. Just a few cool concepts I've seen in the GPU world recently. Sure, matrix multiplications get the headlines because of tensors / deep learning. But don't sleep on the obscure stuff.
the8472 6y ago
+ many proprietary GPU instruction sets
justin66 6y ago
Why do you assume Power will last another 10 years?
sneak 6y ago
What is the SPARC64 use case in Japan? Supercomputing?
rst 6y ago
Depends where you look. Hard to see IBM's z/Architecture dying out in that timeframe (the latest branding for S/360-derived mainframes), for example, and the embedded space is likely to remain an odd bestiary for quite some time.
- monocasa 6y ago
  Embedded is going to become way less of a bestiary, at least in the five digit gate count RISC space. ARC, Xtensa, V850, arguably MIPS, etc. all worked in the "we're cheaper to license than ARM, and will let you modify the core more than ARM will" space. I'm not sure how they maintain that value add when compared to lower end RISC-V cores. I expect half of them to fold, and half of them to turn into consulting ships for RISC-V and fabless design in general.
- projektfu 6y ago
  Isn't z/Architecture just emulated on top of POWER? That's been my impression for a while.
  - monocasa 6y ago
    They share RTL, but it's not just a POWER core with a z/Arch frontend.
  - dfox 6y ago
    You probably mean "TIMI" which is the user-visible ISA of IBM's "midrange" systems (ie. AS/400 or System/i) which was from the start meant as virtual machine ISA that is then mostly AOT transpiled into whatever hardware ISA OS/400 or i5/OS runs on. z/Architecture (S/360, ESA/390, what have you...) is distinct from that and distinct from PowerPC. Modern POWER and z/Architecture CPUs and machines are somewhat similar when you look at the execution units and overall system design, but the ISA is completely different and even the performance profile of the mostly similar CPU is different (z/Architecture is "uber-CISC" with instructions like "calculate sha256 of this megabyte of memory").
    - monocasa 6y ago
justicezyx 6y ago
This is indeed huge. Should open the path for the modernization of the auto chip industry, according to [1], 80% of ADAS chips are based on mips. [1] https://www.globenewswire.com/news-release/2019/02/28/1744607/0/en/Wave-Computing-s-MIPS-Processors-Power-80-of-Today-s-ADAS-Enabled-Automobiles.html https://www.globenewswire.com/news-release/2019/02/28/174460...
steviedotboston 6y ago
so basically the same architecutes that have been widely deployed for the past 20+ years?

This is huge. It looks like the only architectures widely-deployed in ten years will be x86, ARM, Power, and RISC-V (maybe also SPARC64 in Japan, although that's rare in the US).

tyingq 6y ago

The "not ARM based" MCU market might be interesting to watch as well. Not just for RISC-V, but also as ARM MCUs continue to drop in power needs and unit cost.

dragontamer 6y ago

The big innovation in architectures is in the SIMD world. AVX512 (x86 512-bit), SVE (ARM 512-bit), NVidia PTX / SASS (32x32-bit), AMD RDNA (32x32-bit), AMD CDNA (64x32-bit). 64-bit cores (aka: classic CPUs) are looking like a solved problem, and are becoming a commodity. SIMD compute however, remains an open question. NVidia probably leads today, but there seems to be plenty of room for smaller players. Heck, one major company (AMD) is pushing 32x32-bit on one market (6xxx series) and 64x32-bit in another market (MI100 / Supercomputers).

tyingq 6y ago
Fujitsu seems like a leader for SIMD via their A64FX. I wonder if they will ever venture outside of the supercomputing niche.
- dragontamer 6y ago
  SVE is looking like a general-purpose ARM instruction set in the future. I believe the Neoverse V-cores (high-performance) will have access to the SVE instructions for example. So the SVE-SIMD is not necessarily locked to Fujitsu (though Fujitsu's particular implementation is probably crazy good. HBM2 + 512-bit wide and #1 supercomputer in the world and all...)
londons_explore 6y ago
SIMD today is only really helpful with a few usecases. If you want to encode some video, decode some jpegs, or do a physics simulation quicker, it's really going to help. It won't boot Linux any quicker tho. I suspect for consumer uses, SIMD is already used for nearly all the use cases it can be.
- dragontamer 6y ago
  Are you sure about that? The original SIMD-papers in the 1980s show how to compile a Regex into a highly-parallel state machine and then "reduced" (aka: Scan / Prefix-operation: https://en.wikipedia.org/wiki/Prefix_sum https://en.wikipedia.org/wiki/Prefix_sum). A huge amount of operations, such as XML-whitespace removal (aka: SIMD Steam Compacting), Regular Expressions, and more, have been proven ~30 to 40 years ago to benefit from SIMD compute. Yet such libraries don't exist today yet. SIMD compute is highly niche, and clearly today's population is overly focused on deep-learning... without even seeing the easy opportunities of XML parsing or simple regex yet. Further: additional opportunities are being discovered in O(n^2) operations: such as inner-join operations on your typical database. Citations. * For Regular Expressions: Read the 1986 paper "DATA PARALLEL ALGORITHMS". Its an easy read. Hillis / Steele are great writers. They even have the "impossible Linked List" parallelism figured out in there (granted: the nodes are located in such a way that the SIMD-computer can work with the nodes. But... if you had a memory-allocator that worked with their linked-list format, you could very well implement their pointer-jumping approach to SIMD-linked list traversal) * For whitespace folding / removal, see http://www.cse.chalmers.se/~uffe/streamcompaction.pdf http://www.cse.chalmers.se/~uffe/streamcompaction.pdf. They don't cite it as XML-whitespace removal, but it seems pretty obvious to me that it could be used for parallel whitespace removal in O(lg(n)) steps. * Database SIMD: http://www.cs.columbia.edu/~kar/pubsk/simd.pdf http://www.cs.columbia.edu/~kar/pubsk/simd.pdf . Various operations have been proven to be better on SIMD, including "mass binary search" (one binary search cannot be parallelized. But if you have 5000-binary searches operating in parallel, its HIGHLY efficient to execute all 5000 in a weird parallel manner, far faster than you might originally imagine). ---------- SIMD-cuckoo hashing, SIMD-skip lists, etc. etc. There's so many data-structures that haven't really been fleshed out on SIMD yet outside of research settings. They have been proven easy to implement and simple / clean to understand. They're just not widely known yet.
gnufx 6y ago
The V in SVE is for vector, the S isn't for SIMD, and it's length-agnostic; I don't know how similar it is to the RISC-V vector extension. Think CDC, Cray, NEC, not AMD/Intel. I guess the recent innovation in that space is actual matrix multiplication instructions in CPUs.
- dragontamer 6y ago
  Some GPU assembly advancements... * Bpermute and permute. (Pshufb is like permute, a gather operation. Bpermute is the opposite, like a scatter. Bpermute Doesn't exist on x86 yet) * __shared__ memory crossbar: every simd unit can read, or write, to shared memory in parallel per clocktick. The crossbar can also broadcast 1-to-all each clocktick. * Butterfly permute: the fundamental pattern in permutations for a variety of operations. Most noticably for scan, and FFTs. Butterfly networks are closely related to pext and pdep implementation (showing how common that particular permute is). * 8+ way hyperthreads / SMT. GPUs have very bad latency, but very high SMT counteracts that problem well in practice. * PCIe Atomics: perform those compare and swap negotiations over I/O, allowing tight CPU and GPU memory integration. * Crazy RAM. 1000GBps on HBM2. 800GBps over GDDR6x thanks to 2-bits transferred per clock ticks. * Crazy networks. AMD Infinity fabric pushes over 100GB. NVlink is 600GBps. A GPU network link has more bandwidth than a typical CPU's DDR4 RAM bandwidth. * NVidia SASS has the craziest instruction set, the compiler figures out read / write hazards and publishes them in the SASS assembly itself. NVidias ISA decoder + assembler team is doing something crazy here, the likes I haven't seen in any other instruction set ever. * "Ballot" instructions. Its... really hard to explain why these are useful. They just are, lol. Just a few cool concepts I've seen in the GPU world recently. Sure, matrix multiplications get the headlines because of tensors / deep learning. But don't sleep on the obscure stuff.

the8472 6y ago

+ many proprietary GPU instruction sets

justin66 6y ago

Why do you assume Power will last another 10 years?

sneak 6y ago

What is the SPARC64 use case in Japan? Supercomputing?

rst 6y ago

Depends where you look. Hard to see IBM's z/Architecture dying out in that timeframe (the latest branding for S/360-derived mainframes), for example, and the embedded space is likely to remain an odd bestiary for quite some time.

monocasa 6y ago
Embedded is going to become way less of a bestiary, at least in the five digit gate count RISC space. ARC, Xtensa, V850, arguably MIPS, etc. all worked in the "we're cheaper to license than ARM, and will let you modify the core more than ARM will" space. I'm not sure how they maintain that value add when compared to lower end RISC-V cores. I expect half of them to fold, and half of them to turn into consulting ships for RISC-V and fabless design in general.
projektfu 6y ago
Isn't z/Architecture just emulated on top of POWER? That's been my impression for a while.
- monocasa 6y ago
  They share RTL, but it's not just a POWER core with a z/Arch frontend.
- dfox 6y ago
  You probably mean "TIMI" which is the user-visible ISA of IBM's "midrange" systems (ie. AS/400 or System/i) which was from the start meant as virtual machine ISA that is then mostly AOT transpiled into whatever hardware ISA OS/400 or i5/OS runs on. z/Architecture (S/360, ESA/390, what have you...) is distinct from that and distinct from PowerPC. Modern POWER and z/Architecture CPUs and machines are somewhat similar when you look at the execution units and overall system design, but the ISA is completely different and even the performance profile of the mostly similar CPU is different (z/Architecture is "uber-CISC" with instructions like "calculate sha256 of this megabyte of memory").
  - monocasa 6y ago

justicezyx 6y ago

This is indeed huge. Should open the path for the modernization of the auto chip industry, according to [1], 80% of ADAS chips are based on mips. [1] https://www.globenewswire.com/news-release/2019/02/28/1744607/0/en/Wave-Computing-s-MIPS-Processors-Power-80-of-Today-s-ADAS-Enabled-Automobiles.html https://www.globenewswire.com/news-release/2019/02/28/174460...

steviedotboston 6y ago

so basically the same architecutes that have been widely deployed for the past 20+ years?