4 ms·

Interesting, I wasn't familiar with the Whirlwind. Regarding the hardwired control in RISC designs that makes sense. I have a somewhat tangential question - in

Interesting, I wasn't familiar with the Whirlwind. Regarding the hardwired control in RISC designs that makes sense. I have a somewhat tangential question - in doing some Googling about RISC and control units I came across the following from a question on Quora[1]: >"P5 (Pentium) and P6 (Pentium Pro). Note that the control unit was phased out in favour of the reservation station and re-order buffer." >"The control unit with its rule-based, static approach is far too simplistic and would perform poorly in an out-of-order superscalar core design where the code stream is sequential." At first this struck me as odd as I wouldn't have thought that reservation/station and ROB would be mutually exclusive with a control unit but it got me to wondering is the microcoded control unit more of logical entity today that's split between the reservation/station and ROB? Or was this something specific to this Pentium chips. Or is this person just wrong? [1] https://www.quora.com/Why-do-CISC-computer-architecture-tend-to-use-hardwired-control-units https://www.quora.com/Why-do-CISC-computer-architecture-tend...

pwg 6y ago
In that quora answer, the box labeled "control unit" really should have been labeled "scheduler", as it is the unit that would be "scheduling" instructions for execution into the execution units (taking dependencies into account to do so). That "scheduling" is a "control" function, so "control unit" is not wrong, per. se., but there is still going to be a "control unit" even in the reservation station/reorder buffer variant on the right as well. What differs between the two is that the "scheduling" that occurred by the left side "control unit" was instead dispersed into the reservation stations and reorder buffer of the right side diagram. But there will still be a "control unit" handling overall control of the CPU, it is just not given a box and a label in the right side.
- bogomipz 6y ago
  Thanks. I think this is the key idea I was looking to understand: >"What differs between the two is that the "scheduling" that occurred by the left side "control unit" was instead dispersed into the reservation stations and reorder buffer of the right side diagram." Is it a correct mental model then to think about control unit being a logical or "distributed" unit(right side of diagram) instead of a monolithic unit(the left side of diagram)? I'm guessing this "reservation station/reorder buffer variant" of control unit is the predominant one in use in CISC chips these days?
  - pwg 6y ago
    > Is it a correct mental model then to think about control unit being a logical or "distributed" unit(right side of diagram) instead of a monolithic unit(the left side of diagram)? That is a somewhat reasonable interpretation. Just keep in mind that both diagrams are massive simplifications of the actual reality (i.e., the left side diagram likely had a more dispersed control system than the block diagram would lead one to believe). > I'm guessing this "reservation station/reorder buffer variant" of control unit is the predominant one in use in CISC chips these days? It is/has been a popular model (first introduced by IBM in the 360/91 mainframe circa 1967 -- R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units, https://www.cs.virginia.edu/~evans/greatworks/tomasulo.pdf https://www.cs.virginia.edu/~evans/greatworks/tomasulo.pdf) for many designs over the years. As for predominant in CISC chips, that really depends upon what current Intel/AMD CPU's are doing internally, and I've not kept up with their most recent offering's internal designs.
    - bogomipz 6y ago
      Thanks and thanks for the link. I was aware of the Tomasulo algorithm but I don't think I've ever seen the original paper nor did I know it was inherently connected to the IBM OS/360. Cheers.

pwg 6y ago

In that quora answer, the box labeled "control unit" really should have been labeled "scheduler", as it is the unit that would be "scheduling" instructions for execution into the execution units (taking dependencies into account to do so). That "scheduling" is a "control" function, so "control unit" is not wrong, per. se., but there is still going to be a "control unit" even in the reservation station/reorder buffer variant on the right as well. What differs between the two is that the "scheduling" that occurred by the left side "control unit" was instead dispersed into the reservation stations and reorder buffer of the right side diagram. But there will still be a "control unit" handling overall control of the CPU, it is just not given a box and a label in the right side.

bogomipz 6y ago
Thanks. I think this is the key idea I was looking to understand: >"What differs between the two is that the "scheduling" that occurred by the left side "control unit" was instead dispersed into the reservation stations and reorder buffer of the right side diagram." Is it a correct mental model then to think about control unit being a logical or "distributed" unit(right side of diagram) instead of a monolithic unit(the left side of diagram)? I'm guessing this "reservation station/reorder buffer variant" of control unit is the predominant one in use in CISC chips these days?
- pwg 6y ago
  > Is it a correct mental model then to think about control unit being a logical or "distributed" unit(right side of diagram) instead of a monolithic unit(the left side of diagram)? That is a somewhat reasonable interpretation. Just keep in mind that both diagrams are massive simplifications of the actual reality (i.e., the left side diagram likely had a more dispersed control system than the block diagram would lead one to believe). > I'm guessing this "reservation station/reorder buffer variant" of control unit is the predominant one in use in CISC chips these days? It is/has been a popular model (first introduced by IBM in the 360/91 mainframe circa 1967 -- R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units, https://www.cs.virginia.edu/~evans/greatworks/tomasulo.pdf https://www.cs.virginia.edu/~evans/greatworks/tomasulo.pdf) for many designs over the years. As for predominant in CISC chips, that really depends upon what current Intel/AMD CPU's are doing internally, and I've not kept up with their most recent offering's internal designs.
  - bogomipz 6y ago
    Thanks and thanks for the link. I was aware of the Tomasulo algorithm but I don't think I've ever seen the original paper nor did I know it was inherently connected to the IBM OS/360. Cheers.