3 ms·

I know I'm a big dummy, but is this "machine learning built in" (and similarly, for the Apple Silicon M1 "neural engine") really just mean "ALUs with additional

• cma 6y ago
  If it is an instruction thing and not more of a separate coprocessor, it is maybe SIMD on smaller integers for inference (like how AVX512 enables vectorized 8bit integer math, for 64 operations per instruction).
• dragontamer 6y ago
  > really just mean "ALUs with additional multiply/add units"? Well, that's true in general :-) When CPU companies these days say "machine learning" instructions, they *REALLY* mean 8-bit or 16-bit matrix-multiplication acceleration of some kind. Its very vague, but that's what the machine-learning guys care about. * NVidia implements Half-float FP16 4x4 matrix multiplication instructions. * AMD implements INT8, BFloat16, FP16 dot-product instructions. * Intel implements AVX512 INT8 instructions. I don't know the details however What will the Rasp. Pi implement? 4 to 8 MAC instructions/clock. MAC will certainly accelerate matrix-multiplications, but not as much as a proper 4x4 matrix multiplication instruction.
• Salgat 6y ago
  From the article, "It may come in the form of lightweight accelerators possibly 4-8 multiply-accumulates (MACs) per clock cycle." My guess is that they'll likely incorporate something like the Arm Neon architecture extension that significantly improves performance in linear algebra and signal processing.