I'm not sure we're going to see formal proof totally replace standard verification any time soon however when combined with more traditional verification techni

I'm not sure we're going to see formal proof totally replace standard verification any time soon however when combined with more traditional verification techniques it's very effective. It can find interesting bugs very quickly that other methods may have taken significant cycles to find. As it approaches the problem very differently you get a different set of bugs found from it. It's also great for early bring-up work. With a handful of constraints you can start looking at least some aspects of design behaviour without needing an extensive testbench. When I was working on L1 memory system design at arm I used formal tooling extensively to bring up parts of the memory system before the full testbench was available. You may start to see formal only verification on smaller/simpler blocks. E.g. imagine some bus adapter, with a decent set of formal properties that specify the bus functionality you may have to do very little work to verify it with formal tools. There's also the use of SVAs within standard verification. This isn't formal verification but if you've done any formal work you end up with a bunch of new checks you can run in your standard verification flows too, again finding bugs more quickly. You can get nice feedback between the two, develop constraints to enable formal testing, those constraints become assertions in some other verification flow, it finds a violation of the constraint, you realise it needs adapting to cover some extra behaviour and your formal environment is improved (in effect you've found your spec bug). View it as another tool in the toolbox, one that is becoming every more necessary as hardware designs become ever more complex.