They used two 68000s. One was heavily modified at the hardware level to directly execute the simple S370 instructions, the other was a standard 68000 which ran

They used two 68000s. One was heavily modified at the hardware level to directly execute the simple S370 instructions, the other was a standard 68000 which ran standard 68000 code as effectively microcode to emulate complex S370 instructions while the other core was halted. Pretty much any modern RISC CPU could be reasonably easily modified to run RISC-V code. An arm64 one is the obvious candidate. The ZERO register needs to be changed from reg 31 to reg 0 and a whole bunch of addressing mode stuff can be removed. The you need to either add support for RISC-V's "compare and branch" instructions (and rip out the condition code support) or else split the RISC-V instruction in to two arm64 ones (cmp then branch). AMD could do the same with Zen3, but it would be a bigger job and a lot more would need to be ripped out.