What would it take for AMD to support an Risc-V? I recall from the discussion of x86’s inefficiency that it’s often said that decoding instruction formats is bu

What would it take for AMD to support an Risc-V? I recall from the discussion of x86’s inefficiency that it’s often said that decoding instruction formats is but a small amount of silicon space compared to cache and branch prediction systems and those seem to be barely dependent on the instruction format itself.