4 ms·

Also worth mentioning that chips from 20 years ago are built on old fabrication technology, with ginormous transistor sizes (compared to modern CPUs). The RAD75

Also worth mentioning that chips from 20 years ago are built on old fabrication technology, with ginormous transistor sizes (compared to modern CPUs). The RAD750 has a 150nm to 250nm minimum feature sizes, a Ryzen Zen 3 chip has a feature size of 7nm, two orders of magnitude smaller! Feature size is super important in radiation exposed environments because resistance to bit flips from a stray proton (or other charged particles flying around in space) is inversely proportional to the size of your transistors. So small transistors mean they’re more likely to be activated by stray charged particles causing all kinds of interesting and exciting problems (which you don’t want to be debugging from one end of a 12 light minute comms channel).

mlyle 6y ago
> The RAD750 has a 150nm to 250nm minimum feature sizes, a Ryzen Zen 3 chip has a feature size of 7nm, Yup. And while the transistor sizes haven't really shrunk by the 35x that this suggests, they've still shrunk by a lot. And, of course, the area has shrunk by this amount squared. > causing all kinds of interesting and exciting problems Sometimes super exciting. Latchup can turn the whole package into a white-hot parasitic transistor connecting Vcore to ground at low impedance. Rad-hard variants can largely eliminate this possibility.
- wtallis 6y ago
  If we compare the RAD750 against the 5nm Apple A1, the newer chip has about 1660 times as many transistors per mm^2. Minimum feature size (ie. line widths) may not have kept pace with the nanometer-based fab node names, but transistor sizes definitely have.
  - mlyle 6y ago
    Eh. Don't compare the RAD 750. It's better to compare something that's not domain specific and rad hard. Compare the PPC 740, which was ~300,000 transistors/mm^2 at 260nm. Apple M1 is ~130,000,000 transistors/mm^2 at 5nm. (260/5)^2 =~ 2700x, but the actual difference is ~430x. So it's not as bad as line widths, but it still isn't quite keeping pace.
- Florin_Andrei 6y ago
  > a white-hot parasitic transistor connecting Vcore to ground at low impedance In plain English: an internal short-circuit.
  - zelon88 6y ago
    The rabbit hole was worth it... https://en.wikipedia.org/wiki/Latch-up https://en.wikipedia.org/wiki/Latch-up https://en.wikipedia.org/wiki/Single-event_upset https://en.wikipedia.org/wiki/Single-event_upset https://en.wikipedia.org/wiki/Radiation_hardening https://en.wikipedia.org/wiki/Radiation_hardening
- jandrese 6y ago
  This does make one wonder about an architecture that has 4 or more identical processors hooked up to the same inputs and two watchdogs watching them (and each other). If any processor starts disagreeing with the rest it is instantly reset. If any processor starts to draw too much or too little current it is reset. If either watchdog stops responding to the other it is reset. Keeping the working data synchronized would be the real trick. One could imagine all of these CPUs are hooked to a single bank of redundant and ECC stabilized memory, and all access goes through the watchdog processes which will only let through the ones that are in agreement. The end result could be a system that is lighter and faster than the traditional RAD hardened system simply because it's built on a smaller process. The downside is the enormous complexity of the watchdog systems, they would be very expensive to get right. Also, synchronization is one of the hardest problems in computer science. It's basically cache invalidation on steroids.
  - mlyle 6y ago
    > This does make one wonder about an architecture that has 4 or more identical processors hooked up to the same inputs and two watchdogs watching them (and each other). If any processor starts disagreeing with the rest it is instantly reset. If any processor starts to draw too much or too little current it is reset. If either watchdog stops responding to the other it is reset. This is a common set of techniques in critical systems. The smallsat built by students that I mentored didn't have voting, but it had processors with moderately sophisticated watchdogs performing mutual-power-monitoring and simple hardware failsafes. Aerospace control systems often run in lockstep and have voting, etc. > Keeping the working data synchronized would be the real trick. One could imagine all of these CPUs are hooked to a single bank of redundant and ECC stabilized memory, and all access goes through the watchdog processes which will only let through the ones that are in agreement. Typically you make the memory redundant too, and just ensure that input and outputs are common and all code is deterministic. e.g. There's Tandem / HP NonStop which use these techniques. > The end result could be a system that is lighter and faster than the traditional RAD hardened system simply because it's built on a smaller process. Handling upsets by voting makes a lot of sense. But radiation can cause permanent damage of small geometry circuits. And even with fast mechanisms to crowbar power in the event of a latchup, you're not really sure that you'll save the day. It's a great way to handle things on the cheap for cutting edge payloads and research projects, though.
AmericanChopper 6y ago
> a Ryzen Zen 3 chip has a feature size of 7nm The node sizes used in marketing today haven't actually had any relation to feature size for at least 10 years. You can read some of the actual feature details for 7nm on wikipedia. https://en.wikipedia.org/wiki/7_nm_process#7_nm_process_nodes_and_process_offerings https://en.wikipedia.org/wiki/7_nm_process#7_nm_process_node... If "feature size" is the width of a fin, a 7nm feature will typically be ~15nm across and spaced ~15nm apart (ie the center of one transistor is 30nm away from the center of the transistor next to it). It's worth noting that the actual thickness of a transistor isn't strictly the most important factor. Which is why that wiki page shows fin pitch (the width of the transistor plus the space between transistors), because that's the metric that you get transistor density from.

mlyle 6y ago

> The RAD750 has a 150nm to 250nm minimum feature sizes, a Ryzen Zen 3 chip has a feature size of 7nm, Yup. And while the transistor sizes haven't really shrunk by the 35x that this suggests, they've still shrunk by a lot. And, of course, the area has shrunk by this amount squared. > causing all kinds of interesting and exciting problems Sometimes super exciting. Latchup can turn the whole package into a white-hot parasitic transistor connecting Vcore to ground at low impedance. Rad-hard variants can largely eliminate this possibility.

wtallis 6y ago
If we compare the RAD750 against the 5nm Apple A1, the newer chip has about 1660 times as many transistors per mm^2. Minimum feature size (ie. line widths) may not have kept pace with the nanometer-based fab node names, but transistor sizes definitely have.
- mlyle 6y ago
  Eh. Don't compare the RAD 750. It's better to compare something that's not domain specific and rad hard. Compare the PPC 740, which was ~300,000 transistors/mm^2 at 260nm. Apple M1 is ~130,000,000 transistors/mm^2 at 5nm. (260/5)^2 =~ 2700x, but the actual difference is ~430x. So it's not as bad as line widths, but it still isn't quite keeping pace.
Florin_Andrei 6y ago
> a white-hot parasitic transistor connecting Vcore to ground at low impedance In plain English: an internal short-circuit.
- zelon88 6y ago
  The rabbit hole was worth it... https://en.wikipedia.org/wiki/Latch-up https://en.wikipedia.org/wiki/Latch-up https://en.wikipedia.org/wiki/Single-event_upset https://en.wikipedia.org/wiki/Single-event_upset https://en.wikipedia.org/wiki/Radiation_hardening https://en.wikipedia.org/wiki/Radiation_hardening
jandrese 6y ago
This does make one wonder about an architecture that has 4 or more identical processors hooked up to the same inputs and two watchdogs watching them (and each other). If any processor starts disagreeing with the rest it is instantly reset. If any processor starts to draw too much or too little current it is reset. If either watchdog stops responding to the other it is reset. Keeping the working data synchronized would be the real trick. One could imagine all of these CPUs are hooked to a single bank of redundant and ECC stabilized memory, and all access goes through the watchdog processes which will only let through the ones that are in agreement. The end result could be a system that is lighter and faster than the traditional RAD hardened system simply because it's built on a smaller process. The downside is the enormous complexity of the watchdog systems, they would be very expensive to get right. Also, synchronization is one of the hardest problems in computer science. It's basically cache invalidation on steroids.
- mlyle 6y ago
  > This does make one wonder about an architecture that has 4 or more identical processors hooked up to the same inputs and two watchdogs watching them (and each other). If any processor starts disagreeing with the rest it is instantly reset. If any processor starts to draw too much or too little current it is reset. If either watchdog stops responding to the other it is reset. This is a common set of techniques in critical systems. The smallsat built by students that I mentored didn't have voting, but it had processors with moderately sophisticated watchdogs performing mutual-power-monitoring and simple hardware failsafes. Aerospace control systems often run in lockstep and have voting, etc. > Keeping the working data synchronized would be the real trick. One could imagine all of these CPUs are hooked to a single bank of redundant and ECC stabilized memory, and all access goes through the watchdog processes which will only let through the ones that are in agreement. Typically you make the memory redundant too, and just ensure that input and outputs are common and all code is deterministic. e.g. There's Tandem / HP NonStop which use these techniques. > The end result could be a system that is lighter and faster than the traditional RAD hardened system simply because it's built on a smaller process. Handling upsets by voting makes a lot of sense. But radiation can cause permanent damage of small geometry circuits. And even with fast mechanisms to crowbar power in the event of a latchup, you're not really sure that you'll save the day. It's a great way to handle things on the cheap for cutting edge payloads and research projects, though.

AmericanChopper 6y ago

> a Ryzen Zen 3 chip has a feature size of 7nm The node sizes used in marketing today haven't actually had any relation to feature size for at least 10 years. You can read some of the actual feature details for 7nm on wikipedia. https://en.wikipedia.org/wiki/7_nm_process#7_nm_process_nodes_and_process_offerings https://en.wikipedia.org/wiki/7_nm_process#7_nm_process_node... If "feature size" is the width of a fin, a 7nm feature will typically be ~15nm across and spaced ~15nm apart (ie the center of one transistor is 30nm away from the center of the transistor next to it). It's worth noting that the actual thickness of a transistor isn't strictly the most important factor. Which is why that wiki page shows fin pitch (the width of the transistor plus the space between transistors), because that's the metric that you get transistor density from.