4 ms·

I designed and wrote an entire CPU in Verilog in a couple weeks in college. I suspect there is a large difference between wired OR interrupts and something tha

I designed and wrote an entire CPU in Verilog in a couple weeks in college. I suspect there is a large difference between wired OR interrupts and something that can inform all the arm exception levels, IPI's, direct injection into VM's, etc. AKA all the things required to run Linux on a modern Arm core in a reasonable fashion.

monocasa 6y ago
No, like I've wrote shipping to customers interrupt controllers, not a school project. The meat of most of what you're talking about happens in the CPU cores. The interrupt controller just exports "this is the highest priority interrupt" signal based on some signals input, and some interrupt signals that can be triggered off of a memory write (IPIs). The shit's really almost hello world HDL. VM passthrough is just a parrallel set of comparison logic and another "this is the highest priority signal" to the CPU core. But you didn't address the important part, that your calculus is wrong on the support time frames. They aren't supporting these things for 20 years. And I guarantee you they've cranked the numbers, so much of these designs are focused at taking a fraction of a penny off of each shipped unit. Adding to that, the underlying piece is that they don't care about the bootloader being nice, and 'they' is several entities with their own goals and requirements. The chips in SBCs are almost entirely leftovers. They made too much for some big customer that for whatever reason didn't use the whole batch, and went to sell them off at fire sale prices. Then some incredibly cost conscious shop buys them up, sticks them on cost reduced dev boards with the custom kernel and calls it a day. The chip company doesn't care because the major customers don't care. The major customers (ie. the integrator for who the chip was designed in the first place) don't care because they just want a Linux kernel booting, and don't care how that happens. The SBC customer doesn't care because they're already running on such low margins they can't afford to do anything to software as it is.

monocasa 6y ago

No, like I've wrote shipping to customers interrupt controllers, not a school project. The meat of most of what you're talking about happens in the CPU cores. The interrupt controller just exports "this is the highest priority interrupt" signal based on some signals input, and some interrupt signals that can be triggered off of a memory write (IPIs). The shit's really almost hello world HDL. VM passthrough is just a parrallel set of comparison logic and another "this is the highest priority signal" to the CPU core. But you didn't address the important part, that your calculus is wrong on the support time frames. They aren't supporting these things for 20 years. And I guarantee you they've cranked the numbers, so much of these designs are focused at taking a fraction of a penny off of each shipped unit. Adding to that, the underlying piece is that they don't care about the bootloader being nice, and 'they' is several entities with their own goals and requirements. The chips in SBCs are almost entirely leftovers. They made too much for some big customer that for whatever reason didn't use the whole batch, and went to sell them off at fire sale prices. Then some incredibly cost conscious shop buys them up, sticks them on cost reduced dev boards with the custom kernel and calls it a day. The chip company doesn't care because the major customers don't care. The major customers (ie. the integrator for who the chip was designed in the first place) don't care because they just want a Linux kernel booting, and don't care how that happens. The SBC customer doesn't care because they're already running on such low margins they can't afford to do anything to software as it is.