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I wish there were a good tutorial about FPGA development using version control tools. It’s easy having Vivado project with couple source files, but totally unco

by lnsru 6y ago

I wish there were a good tutorial about FPGA development using version control tools. It’s easy having Vivado project with couple source files, but totally uncool using block design. Especially with my own IP blocks.

liaukovv 6y ago
Does it make sense to use schematic designs outside of ide context? You dould export them to proper hdl and check that in
Ballas 6y ago
I find vivado will often break my project (usually the axi bus config breaks, and I have not found any way to fix it). The best solution I have found is to use TCL to regenerate the project. You can generate a TCL script of your existing project. I have not tried it, but you might be able to use normal version control tools like git with the TCL script - the usefulness will depend on if things stay in the same order after an update.
- gpanders 6y ago
  I have tried both versioning the entire "raw" block design files and it is a mess. Vivado creates a ton of files and it's not clear which ones you need in version control in order to regenerate the BD from a fresh clone, and many of the files that you do need get modified anytime the block design is used to build the design which causes git to report file modifications. All in all, I don't recommend it. However, managing a Tcl script is very doable, and this is my preferred method now. This has some drawbacks too of course -- you have to ensure that you use the same arguments to the `create_bd_tcl` command every time you update your script, and if you need to make any modifications to the script then you need to have a process for doing that. But it's much better than the alternative.
  - jeffreyrogers 6y ago
    This is pretty much what we settled on where I work as well after experiencing the problems you mentioned in your first paragraph.
jleahy 6y ago
My advice would be to use a tcl build script in non-project mode, check in your tcl script and verilog files and don't use block based design or 'IP' based design.

by lnsru 6y ago

liaukovv 6y ago

Does it make sense to use schematic designs outside of ide context? You dould export them to proper hdl and check that in

Ballas 6y ago

I find vivado will often break my project (usually the axi bus config breaks, and I have not found any way to fix it). The best solution I have found is to use TCL to regenerate the project. You can generate a TCL script of your existing project. I have not tried it, but you might be able to use normal version control tools like git with the TCL script - the usefulness will depend on if things stay in the same order after an update.

gpanders 6y ago
I have tried both versioning the entire "raw" block design files and it is a mess. Vivado creates a ton of files and it's not clear which ones you need in version control in order to regenerate the BD from a fresh clone, and many of the files that you do need get modified anytime the block design is used to build the design which causes git to report file modifications. All in all, I don't recommend it. However, managing a Tcl script is very doable, and this is my preferred method now. This has some drawbacks too of course -- you have to ensure that you use the same arguments to the `create_bd_tcl` command every time you update your script, and if you need to make any modifications to the script then you need to have a process for doing that. But it's much better than the alternative.
- jeffreyrogers 6y ago
  This is pretty much what we settled on where I work as well after experiencing the problems you mentioned in your first paragraph.

jleahy 6y ago

My advice would be to use a tcl build script in non-project mode, check in your tcl script and verilog files and don't use block based design or 'IP' based design.