It might have made things simpler. From memory there was also a VU compiler that would take a single stream of instructions and then try to interleave the the

It might have made things simpler. From memory there was also a VU compiler that would take a single stream of instructions and then try to interleave the the 'left/right' instructions of the VLIW in the most efficient orders. It never was quite as good as hand coding - which is something kind of satisfying once you've memorized the stats of the entire ISA. One half of the instruction word was mostly devoted to vector instructions which would each have a 4 cycle latency, and a single cycle throughput, to say, multiple one 4 word vector of floats with another. The other half had the kitchen sink, like trancendental functions (sin/cos/tan/etc), divide (x/y, 1/x), etc. However an instruction would stall if a calculation was depending on a register whose calculation was still in flight. So if an instruction has a latency of 4 cycles, you could interleave 4 similar calculations on more of the dataset in parallel. So in 4 cycles, you could start 16 float calculations, and by the 8th cycle, they would be available. Though likely you'd be looping with something like Duff's device to maximize throughput. It would also mean you might use the vector calculations with a taylor series, in preference to the sine instruction which had a latency of something like 15 cycles.