If you implement a multiplexer with logic gates, you'd probably do something like `(A and SEL_A) or (B and SEL_B) or (C and SEL_C) or (D and SEL_D)` where A-D a

If you implement a multiplexer with logic gates, you'd probably do something like `(A and SEL_A) or (B and SEL_B) or (C and SEL_C) or (D and SEL_D)` where A-D are the inputs and SEL* are the select lines. Using De Morgan's law, the gates could all be NAND gate. You'd have four 2-input NAND gates (4 transistors each) and a 4-input NAND gate (8 transistors), for a total of 24 transistors if I counted correctly. Using four transmission gates (2 transistors each) would only be 8 transistors. (There are various other tradeoffs I won't get into.) If you didn't need the SEL lines elsewhere, you could fold the decoding into the multiplexer, eliminating the decoding gates, but the multiplexer still comes out ahead. (And thanks for letting me know about the typo. It's nice to know someone reads the footnotes :-)