3 ms·

You say this: > Although a multiplexer can be built with standard logic gates, the implementation with transmission gates is more efficient. But why is that?

• kens 6y ago
  If you implement a multiplexer with logic gates, you'd probably do something like `(A and SEL_A) or (B and SEL_B) or (C and SEL_C) or (D and SEL_D)` where A-D are the inputs and SEL* are the select lines. Using De Morgan's law, the gates could all be NAND gate. You'd have four 2-input NAND gates (4 transistors each) and a 4-input NAND gate (8 transistors), for a total of 24 transistors if I counted correctly. Using four transmission gates (2 transistors each) would only be 8 transistors. (There are various other tradeoffs I won't get into.) If you didn't need the SEL lines elsewhere, you could fold the decoding into the multiplexer, eliminating the decoding gates, but the multiplexer still comes out ahead. (And thanks for letting me know about the typo. It's nice to know someone reads the footnotes :-)
• dfox 6y ago
  Because transmission gate literally are two transistors. Standard two input logic gate contains four. So for example you can build two to one multiplexer from two transmission gates for total of four transistors while implementing the same function from standard totem-pole logic would require at least three gates totaling 12 transistors. (In both cases assuming you already have complementary control input, which you usually either have or can share with something. This kind of sharing optimization is the reason why transmission gate usually has complementary input and does not include the inverter internally)