> Imagine just loading the program into 2D/3D registers and having it compute the result in a single cycle. You mean like SSE extensions in Intel CPUs, which c

> Imagine just loading the program into 2D/3D registers and having it compute the result in a single cycle. You mean like SSE extensions in Intel CPUs, which can operate at 64 bytes at a time, potentially doing 64 operations in a single cycle? Or FPGAs, which can have an arbitrary wide registers -- I have seen a design where entire video scanline, 600+ points, is processed in one cycle? Or video cards, which have multiple parallel executors -- a high-end NVIDIA card can process 64x64 pixels in parallel, with each pixel getting its own little execution core. Or maybe famous Cray 1 machine [0], which had a vector instructions, such as "a single instruction a(1..1000000) = addv b(1..1000000), c(1..1000000)" Or maybe a Connection Machine? It sounds as close to 3-D machine as you can make it -- it even had 3-D shape with bits arranged in cube [1]: > The CM-1, depending on the configuration, has as many as 65,536 individual processors, each extremely simple, processing one bit at a time. CM-1 and its successor CM-2 take the form of a cube 1.5 meters on a side, divided equally into eight smaller cubes. Your say that "no one has ever built these higher dimensional registers" -- but as you can see, there are plenty of examples one can come up with. It is entirely possible that your idea is different from all of these, but it is not clear how. I think your website would benefit greatly from the comparison with those other computing devices, as well as more details as to what this "tree architecture" looks like -- how many ALUs, memory blocks, instruction decoders etc.. do you want to have and how are they interconnected. [0] https://en.wikipedia.org/wiki/Cray-1 https://en.wikipedia.org/wiki/Cray-1 [1] https://en.wikipedia.org/wiki/Connection_Machine https://en.wikipedia.org/wiki/Connection_Machine