36 ms·

Machine Learning for Computer Architecture

97 points by tmfi 6y ago

RcouF1uZ4gsC 6y ago
> In “Apollo: Transferable Architecture Exploration”, we present the progress of our research on ML-driven design of custom accelerators. AI is now designing better hardware to run AI which will be able to design even better hardware to run AI on...
- haskellandchill 6y ago
  When the AI realizes its purpose is to make a better AI.
- trepetti 6y ago
  Just to calm your nerves: place and route algorithms are often classical AI anyway, the things that is changing is what still is and isn't referred to as "AI". The cool thing about this work is that it is looking at higher level parameters about layout instead of the kind of heuristic algorithms you see in APR. Would be cool to see this in tools one day.
- carwyn 6y ago
  Skynet is coming ...
- skybrian 6y ago
  But since it only speeds up part of the design process, they can’t build the hardware much faster than before and cycle time is very slow. If you’re going to worry about this at all, you should be a lot more worried about AI-designed software.
choletentent 6y ago
This article should be censored for those less than 18 years old.
- rubatuga 6y ago
  Lolol the violin plots
danbmil99 6y ago
Can anyone say the singularity is upon us?
- chromanoid 6y ago
  No. Why not value an achievement as is. "AI"/Computer assisted chip design is great.
alecco 6y ago
Are there available AI accelerators on the market at the same level of Google's? I worry we are being locked out of compute capacity. I worry these corporations did a hostile acquisition of all the talent and critical infrastructure and we are left out. And new competitors have such an uphill battle it will be almost impossible to catch up.
- UncleOxidant 6y ago
  You already needed a corporation just to create a regular, but state of the art general purpose processor. You're not going to do what Intel or Samsung does in your garage. Sure, with something like RISC-V you can design a processor and implement it in an FPGA, but that's going to run a lot slower than a processor that is a full-custom design. There are some smallish competitors in the AI accelerator space (Groq and Graphcore come to mind) that are trying to innovate architecturally, but I suspect the door is closing for these companies for the reasons you suggest. The ones with some good ideas will likely be bought out by the likes of Google and Microsoft.
  - deleted 6y ago
    [deleted]
  - alecco 6y ago
    There are big players capable of opening it up like Philips, Sony, IBM, Microsoft, and several more. Or even if, in a weird twist of fate, China embraces an open hardware alliance. But it's looking very, very bad as things are right now.
    - UncleOxidant 6y ago
      China is already a big player in the RISC-V space and will likely dominate there. Ironically, this is at least partially due to the policies of the previous US Administration which is driving China to adopt the open RISC-V ISA so that they're not frozen out of US technology. But still, these are large players with a lot of money (gov funding in China's case). > There are big players capable of opening it up like Philips, Sony, IBM, Microsoft You forget Apple which with the M1 has proven that they can even outdo Intel. But again, Apple has a lot of $Billions to throw around. Microsoft seems to possibly also be making some processor moves, but we'll see how that works out (and again, $Billions to throw around)
Schoolmeister 6y ago
"However, the manifold of architecture search generally contains many points for which there is no feasible mapping from software to hardware." I'm having some trouble understanding how this manifests itself. Can someone help me with this by e.g. providing a toy example?
- jdale27 6y ago
  It means the ML algorithm can propose designs that do well on the objective function (e.g. improved runtime), but can't actually be constructed. They give the example of designs that have more memory than can actually fit on the chip.
  - Schoolmeister 6y ago
    Yes I understand that, but if that is what is meant I find the wording to be somewhat strange. They mention not being able to find a "feasible mapping from software to hardware", and later on "some of the constraints may not be properly formulated into the optimization, and so the compiler may not find a feasible software mapping for the target hardware". So the problem is that there is no software mapping, which I understand to be the mapping of compiler instructions to the underlying hardware. It looks like I'm missing something. Is this the same as saying that the hardware design is not feasible?
    - londons_explore 6y ago
      I imagine they have a basic design in verilog with various tunable parameters (memory size, clock speed, how many instructions to issue at once). They also have a way to run that hardware in a simulator and see how quickly it could train some network. The ML optimization problem is to come up with a bunch of constants which performs well, but also compiles into a manufacturable chip. Clearly setting the clock speed to 9999Ghz isn't that...
      - winterismute 6y ago
        But what I don't understand is: they claim their approch side-steps the "unfeasible" configs, which is and would be a major achievement, however I don't see how the unfeasibility is captured in their evaluation function, which measures mostly runtime and area, and none of them give negative clear negative rewards to unfeasibility since for example, as you noticed, unbuildable configs would return high runtime... Area might correlate negatively, but at that point I don't see how some methods work (eg evolutionary algorithm) and others really don't... Did you understand that part?

97 points by tmfi 6y ago

> In “Apollo: Transferable Architecture Exploration”, we present the progress of our research on ML-driven design of custom accelerators. AI is now designing better hardware to run AI which will be able to design even better hardware to run AI on...

haskellandchill 6y ago
When the AI realizes its purpose is to make a better AI.
trepetti 6y ago
Just to calm your nerves: place and route algorithms are often classical AI anyway, the things that is changing is what still is and isn't referred to as "AI". The cool thing about this work is that it is looking at higher level parameters about layout instead of the kind of heuristic algorithms you see in APR. Would be cool to see this in tools one day.
carwyn 6y ago
Skynet is coming ...
skybrian 6y ago
But since it only speeds up part of the design process, they can’t build the hardware much faster than before and cycle time is very slow. If you’re going to worry about this at all, you should be a lot more worried about AI-designed software.

choletentent 6y ago

This article should be censored for those less than 18 years old.

rubatuga 6y ago
Lolol the violin plots

danbmil99 6y ago

Can anyone say the singularity is upon us?

chromanoid 6y ago
No. Why not value an achievement as is. "AI"/Computer assisted chip design is great.

alecco 6y ago

Are there available AI accelerators on the market at the same level of Google's? I worry we are being locked out of compute capacity. I worry these corporations did a hostile acquisition of all the talent and critical infrastructure and we are left out. And new competitors have such an uphill battle it will be almost impossible to catch up.

UncleOxidant 6y ago
You already needed a corporation just to create a regular, but state of the art general purpose processor. You're not going to do what Intel or Samsung does in your garage. Sure, with something like RISC-V you can design a processor and implement it in an FPGA, but that's going to run a lot slower than a processor that is a full-custom design. There are some smallish competitors in the AI accelerator space (Groq and Graphcore come to mind) that are trying to innovate architecturally, but I suspect the door is closing for these companies for the reasons you suggest. The ones with some good ideas will likely be bought out by the likes of Google and Microsoft.
- deleted 6y ago
  [deleted]
- alecco 6y ago
  There are big players capable of opening it up like Philips, Sony, IBM, Microsoft, and several more. Or even if, in a weird twist of fate, China embraces an open hardware alliance. But it's looking very, very bad as things are right now.
  - UncleOxidant 6y ago
    China is already a big player in the RISC-V space and will likely dominate there. Ironically, this is at least partially due to the policies of the previous US Administration which is driving China to adopt the open RISC-V ISA so that they're not frozen out of US technology. But still, these are large players with a lot of money (gov funding in China's case). > There are big players capable of opening it up like Philips, Sony, IBM, Microsoft You forget Apple which with the M1 has proven that they can even outdo Intel. But again, Apple has a lot of $Billions to throw around. Microsoft seems to possibly also be making some processor moves, but we'll see how that works out (and again, $Billions to throw around)

Schoolmeister 6y ago

"However, the manifold of architecture search generally contains many points for which there is no feasible mapping from software to hardware." I'm having some trouble understanding how this manifests itself. Can someone help me with this by e.g. providing a toy example?

jdale27 6y ago
It means the ML algorithm can propose designs that do well on the objective function (e.g. improved runtime), but can't actually be constructed. They give the example of designs that have more memory than can actually fit on the chip.
- Schoolmeister 6y ago
  Yes I understand that, but if that is what is meant I find the wording to be somewhat strange. They mention not being able to find a "feasible mapping from software to hardware", and later on "some of the constraints may not be properly formulated into the optimization, and so the compiler may not find a feasible software mapping for the target hardware". So the problem is that there is no software mapping, which I understand to be the mapping of compiler instructions to the underlying hardware. It looks like I'm missing something. Is this the same as saying that the hardware design is not feasible?
  - londons_explore 6y ago
    I imagine they have a basic design in verilog with various tunable parameters (memory size, clock speed, how many instructions to issue at once). They also have a way to run that hardware in a simulator and see how quickly it could train some network. The ML optimization problem is to come up with a bunch of constants which performs well, but also compiles into a manufacturable chip. Clearly setting the clock speed to 9999Ghz isn't that...
    - winterismute 6y ago
      But what I don't understand is: they claim their approch side-steps the "unfeasible" configs, which is and would be a major achievement, however I don't see how the unfeasibility is captured in their evaluation function, which measures mostly runtime and area, and none of them give negative clear negative rewards to unfeasibility since for example, as you noticed, unbuildable configs would return high runtime... Area might correlate negatively, but at that point I don't see how some methods work (eg evolutionary algorithm) and others really don't... Did you understand that part?