4 ms·
Forth SoC Written in VHDL
- transfire 6y agoCan this run on a VDHL simulator?
- howerj 6y agoYes, although you will only get waveforms as an output. There is a fully interactive GUI simulator (type "make gui-run" to build it and run it), and a command line simulator as well (just type "make run").
- UncleOxidant 6y agoI wonder if this would fit in a Lattice ICE40 FPGA so that Xilinx ISE could be avoided (very buggy) and open source tools like Yosys could be used instead.
- samlittlewood 6y agoIt will fit in an 8K easily. There was a version of the j1 (that this was based on) running on an IceStick with a 1K part. https://www.excamera.com/sphinx/article-j1a-swapforth.html https://www.excamera.com/sphinx/article-j1a-swapforth.html
- howerj 6y agoIt should fit, as you said, but the last time I tried it the VHDL front-end for Yosys was not up to it. That might have changed as it was a few years ago.
- samlittlewood 6y agoIt is (I think) much better now - it is ghdl as a plugin synthesising to yosys IR. The nightlies from https://github.com/YosysHQ/fpga-toolchain https://github.com/YosysHQ/fpga-toolchain have it all ready to go.
- lozanodiego 6y agoLooks interesting, it is known that J1 is very tiny, how many can fit in the Spartan-6 XC6LX16 mentioned, do you have plan of create a multi-core system with this?
- digiou 6y agoSilly idea, is there any Lisp SoC, like the famed Lisp machines?
- LargoLasskhyfv 6y agoBuild one. Like this: https://en.wikipedia.org/wiki/SECD_machine https://en.wikipedia.org/wiki/SECD_machine Or maybe use that SoC with its FORTH as microcode to implement SECD on top of it. Or look into https://github.com/kanaka/mal https://github.com/kanaka/mal & https://en.wikipedia.org/wiki/POP-11 https://en.wikipedia.org/wiki/POP-11 for matching and mixing.
- jecel 6y agohttps://github.com/lisper/cpus-caddr https://github.com/lisper/cpus-caddr
- analognoise 6y agoI've been considering attempting something like this with Verilator output which is mixed into a GUI produced by QT. This is truly awesome. I can't wait to play with it!
- howerj 6y agoI almost got VHDL STDIN/STDOUT <-> UART <-> H2 core working, which would have allowed you to interact at run time with the VHDL simulation, but I do not think it is possible to do without using non-standard extensions, which is a shame. The attempt is still in "tb.vhd" and can be turned on by modifying "tb.cfg". I was quite impressed that I managed to get a VHDL program that could process a text file at run time so I did not have to keep compiling it.