Its always a trade-off: you have to balance the raw area of packed memory cell rows against all the „support“ fluff: column precharge circuitry, readout buffers

Its always a trade-off: you have to balance the raw area of packed memory cell rows against all the „support“ fluff: column precharge circuitry, readout buffers, adress decoders, etc. I am also unsure whether non-uniform random access times would break some of the abstractions about RAM memory as well. In NAND flash that sort of page-bank parallelism is integrated, since operations are slow.