The approaches I am referring to are indeed oversampled and occur in a "bump in the wire" or on a parallel data path. Moreover, the oversampling occurs at a mu

The approaches I am referring to are indeed oversampled and occur in a "bump in the wire" or on a parallel data path. Moreover, the oversampling occurs at a much higher frequency than the maximum counter frequency of the FPGA -- each clock period is divided into a fractional offset from the rising edge by the capacitative divider or delay line. It is not uncommon at all for dedicated PTP/NTP hardware to implement synchronization and timestamping in this way, even commodity NICs supporting hardware timestamping often implement it on at least a parallel data path.