3 ms·

> How is instead dedicating a single core a worse solution? It is pretty much guaranteed to perform worse, if that's what you mean. Is it worth the effort and

> How is instead dedicating a single core a worse solution? It is pretty much guaranteed to perform worse, if that's what you mean. Is it worth the effort and extra complexity? Probably not. The timestamping jitter with an FPGA would probably be on the order of tens of nanoseconds while we're talking microseconds with a software solution. > There are no gains from custom hardware as network variability would mask them. I _think_ multiple cascaded jitters in a system add with the square root of the sum of squares, so there would still be an improvement. Consider a system where you had 10 microseconds of inherent jitter, then you added another 10 microseconds on top of that. The total is not 10 microseconds - it would be 14.

lmilcin 6y ago
> Is it worth the effort and extra complexity? Probably not. That's pretty much definition of a worse solution.
- Unklejoe 6y ago
  Not necessarily when it comes to something like HFT, where they do things like run point to point microwave links to reduce latency by microseconds.
1_person 6y ago
The precision achievable with FPGAs is well beyond 10s of nanoseconds. The high rate transceivers are used with capacitative dividers or internal signal propagation delays defining the reference intervals for time to digital conversion in extreme accuracy applications, these and similar approaches yield precision to picosecond scale and beyond.
- Unklejoe 6y ago
  Right, but Ethernet timestamping usually occurs on a symbol or byte level inside the MAC, so for GigE, you're looking at 8 nanoseconds per symbol. This could be improved by oversampling the symbols, but at least with GigE, there's (I think) 4 cycles of uncertainty each time the link comes up due to how the clocking agreement between master/slave is established. It's also somewhat difficult to run large counters faster than a few hundred MHz inside of an FPGA. I've worked with systems that use two different clocks - one small counter for Ethernet timestamping, and another main clock, with a periodic latching between the two to correlate them, but it's uncommon. There's also the fact that most PHYs operate by having a FIFO with data being clocked in and clocked out on different clock domains. The way I understand it, the PHY FIFO fills up half way, and only then does it start draining into the MAC. This is to allow for oscillator frequency errors between each device. This is also why there's a maximum frame size and max oscillator tolerance specified for Ethernet - so that this FIFO doesn't under or overrun before the entire frame is received. I think sync-e can improve this quite a bit. Of course, FPGAs themselves are capable of much tighter timings, but in practice, it's usually implemented this way.
  - 1_person 6y ago
    The approaches I am referring to are indeed oversampled and occur in a "bump in the wire" or on a parallel data path. Moreover, the oversampling occurs at a much higher frequency than the maximum counter frequency of the FPGA -- each clock period is divided into a fractional offset from the rising edge by the capacitative divider or delay line. It is not uncommon at all for dedicated PTP/NTP hardware to implement synchronization and timestamping in this way, even commodity NICs supporting hardware timestamping often implement it on at least a parallel data path.

lmilcin 6y ago

> Is it worth the effort and extra complexity? Probably not. That's pretty much definition of a worse solution.

Unklejoe 6y ago
Not necessarily when it comes to something like HFT, where they do things like run point to point microwave links to reduce latency by microseconds.

1_person 6y ago

The precision achievable with FPGAs is well beyond 10s of nanoseconds. The high rate transceivers are used with capacitative dividers or internal signal propagation delays defining the reference intervals for time to digital conversion in extreme accuracy applications, these and similar approaches yield precision to picosecond scale and beyond.

Unklejoe 6y ago
Right, but Ethernet timestamping usually occurs on a symbol or byte level inside the MAC, so for GigE, you're looking at 8 nanoseconds per symbol. This could be improved by oversampling the symbols, but at least with GigE, there's (I think) 4 cycles of uncertainty each time the link comes up due to how the clocking agreement between master/slave is established. It's also somewhat difficult to run large counters faster than a few hundred MHz inside of an FPGA. I've worked with systems that use two different clocks - one small counter for Ethernet timestamping, and another main clock, with a periodic latching between the two to correlate them, but it's uncommon. There's also the fact that most PHYs operate by having a FIFO with data being clocked in and clocked out on different clock domains. The way I understand it, the PHY FIFO fills up half way, and only then does it start draining into the MAC. This is to allow for oscillator frequency errors between each device. This is also why there's a maximum frame size and max oscillator tolerance specified for Ethernet - so that this FIFO doesn't under or overrun before the entire frame is received. I think sync-e can improve this quite a bit. Of course, FPGAs themselves are capable of much tighter timings, but in practice, it's usually implemented this way.
- 1_person 6y ago
  The approaches I am referring to are indeed oversampled and occur in a "bump in the wire" or on a parallel data path. Moreover, the oversampling occurs at a much higher frequency than the maximum counter frequency of the FPGA -- each clock period is divided into a fractional offset from the rising edge by the capacitative divider or delay line. It is not uncommon at all for dedicated PTP/NTP hardware to implement synchronization and timestamping in this way, even commodity NICs supporting hardware timestamping often implement it on at least a parallel data path.