Irq accounting depends on architecture and code usage, e.g. like some kind of barrier (serializing) before the RDTSC. on newer x86_64 the accounting code is ar

Irq accounting depends on architecture and code usage, e.g. like some kind of barrier (serializing) before the RDTSC. on newer x86_64 the accounting code is around 100-200 cycles, so not a big deal, interrupt return and exit code is more than that (save context, load new context etc.). The RDTSC and fence timings (Latency, Reciprocal throughput) [0]: AMD Zen 1 SFENCE 4 ~20 LFENCE 1 0.25 MFENCE 7 ~70 RDTSC 37 36 AMD Zen 2 SFENCE 1 1 LFENCE 1 11 MFENCE 7 ~78 RDTSC 37 37 AMD Zen 3 SFENCE 1 1 LFENCE 1 10 MFENCE 6 ~60 RDTSC 44 36 Intel Haswell LFENCE 2 4 MFENCE 3 33 SFENCE 2 5 RDTSC 15 24 Intel Broadwell LFENCE 2 4 MFENCE 3 33 SFENCE 2 6 RDTSC 15 24 Intel Skylake LFENCE 2 4 MFENCE 4 33 SFENCE 2 6 RDTSC 20 25 Intel Skylake-X LFENCE 2 4 MFENCE 4 33 SFENCE 2 6 RDTSC 20 25 Intel Coffee Lake LFENCE 2 4 MFENCE 4 33 SFENCE 2 6 RDTSC 20 25 [0] https://www.agner.org/optimize/instruction_tables.pdf https://www.agner.org/optimize/instruction_tables.pdf