4 ms·

Reminds me of the PS/2 CELL Architecture, with the SPUs having limited local memory, and needing to DMA stuff around in a streaming fashion to build up larger p

Reminds me of the PS/2 CELL Architecture, with the SPUs having limited local memory, and needing to DMA stuff around in a streaming fashion to build up larger programs.

rbanffy 6y ago
The Cell was a pain to program because of that hateful memory architecture. The anemic PowerPC CPUs didn't help much either. Nothing really prevents an architecture where part of the address space is core-local (with low latency) and not directly accessible from other cores, and the rest points to a (much higher latency) shared memory pool. I have a feeling this would be much nicer to program than a Cell or the average GPU.
- jabl 6y ago
  > Nothing really prevents an architecture where part of the address space is core-local (with low latency) and not directly accessible from other cores, and the rest points to a (much higher latency) shared memory pool. I have a feeling this would be much nicer to program than a Cell or the average GPU. Many GPU's have this kind of local scratchpad memory. Nvidia GPU's even allows the programmer to partition the local SRAM between the scratchpad memory (called shared memory in CUDA docs) and L1 cache.
  - rbanffy 6y ago
    It's a shame nobody came up with an OS that runs entirely on a GPU.
    - fire7000 6y ago
      It's possible a GPU's instruction set isn't sufficient for what a general purpose OS kernel would require
- breatheoften 6y ago
  Seems like the way to go ... maybe even 3 layers of memory -- core local memory, memory that provides shared reader and writer consistency, and memory that provides shared reader, single writer consistency (for ownership transfers). Maybe the second form doesn't actually need to exist at all? Minimizing ownership transfer cost across hardware elements seems like a fundamental concept to me that future architectures will need to specifically optimize in order to maximize the benefits that can be reaped from "task specific" hardware. The more cores we add the more we have to gain by allowing them to be different from each other I think ...
- djmips 6y ago
  Nevertheless people were able to harness the Cell for good performance. It took a re-think and I am not denigrating your experience but our experience was that we benefited everywhere when we reorganized our data and algorithms around the SPUs.
als0 6y ago
That was the PS3.

Reminds me of the PS/2 CELL Architecture, with the SPUs having limited local memory, and needing to DMA stuff around in a streaming fashion to build up larger programs.

rbanffy 6y ago

The Cell was a pain to program because of that hateful memory architecture. The anemic PowerPC CPUs didn't help much either. Nothing really prevents an architecture where part of the address space is core-local (with low latency) and not directly accessible from other cores, and the rest points to a (much higher latency) shared memory pool. I have a feeling this would be much nicer to program than a Cell or the average GPU.

jabl 6y ago
> Nothing really prevents an architecture where part of the address space is core-local (with low latency) and not directly accessible from other cores, and the rest points to a (much higher latency) shared memory pool. I have a feeling this would be much nicer to program than a Cell or the average GPU. Many GPU's have this kind of local scratchpad memory. Nvidia GPU's even allows the programmer to partition the local SRAM between the scratchpad memory (called shared memory in CUDA docs) and L1 cache.
- rbanffy 6y ago
  It's a shame nobody came up with an OS that runs entirely on a GPU.
  - fire7000 6y ago
    It's possible a GPU's instruction set isn't sufficient for what a general purpose OS kernel would require
breatheoften 6y ago
Seems like the way to go ... maybe even 3 layers of memory -- core local memory, memory that provides shared reader and writer consistency, and memory that provides shared reader, single writer consistency (for ownership transfers). Maybe the second form doesn't actually need to exist at all? Minimizing ownership transfer cost across hardware elements seems like a fundamental concept to me that future architectures will need to specifically optimize in order to maximize the benefits that can be reaped from "task specific" hardware. The more cores we add the more we have to gain by allowing them to be different from each other I think ...
djmips 6y ago
Nevertheless people were able to harness the Cell for good performance. It took a re-think and I am not denigrating your experience but our experience was that we benefited everywhere when we reorganized our data and algorithms around the SPUs.

als0 6y ago

That was the PS3.