3 ms·

Are any of those figures public? I did a cursory search but couldn't find them so I went with slightly silly clickbait on the rationale that it was an order of

Are any of those figures public? I did a cursory search but couldn't find them so I went with slightly silly clickbait on the rationale that it was an order of magnitude less silly than the other comparisons being made in the thread. I stand by that: as "benchmarks," a bit adder is much closer to a PLL divider than a 64 bit full adder in a CPU cycle. I fully agree that there's another order of magnitude before the comparison starts to become apples-to-apples, or bit-adders to bit-adders, but you're going to have to help with the search if you want to see it happen.

mlyle 6y ago
What figures, exactly? Here, we're discussing a paper characterizing the current version of the process first with ring oscillators and measured delays through a single cell, and then with a serial bit adder, so.. if you mean those, yes?
- jjoonathan 6y ago
  I mean can you find the bit adder figures for, say, TSMC N7 or N5? I poked around google scholar and wikipedia for a few minutes before giving up and hoping that someone up with the times would know exactly where to look.
  - mlyle 6y ago
    No. Those are subject to NDA, but are broadly similar in fmax and prop time under reasonable voltages. I think it's exciting here that they're dicking around with new technologies in their infancy, and in a few coarse design changes of cells went from 60% of CMOS leading edge to about the same numbers. Of course, total system power, etc, is atrocious, considering that this is cryogenic, etc. You need a lot of logic before this could come ahead in efficiency.
    - jjoonathan 6y ago
      > No. Those are subject to NDA Yeah, that's what I thought and why I settled for a less accurate comparison. > I think it's exciting I think it's exciting, too. The extent of my claims is "no, this does not mean 100GHz LN2 CPUs in a few years." I did not intend these remarks to be meaningful to chip designers, only to CPU consumers who see "GHz" and think "CPU clock speeds." The leverage of having a slightly better fundamental device is extraordinary. We should spare no expense looking for them and leave no stone unturned.

mlyle 6y ago

What figures, exactly? Here, we're discussing a paper characterizing the current version of the process first with ring oscillators and measured delays through a single cell, and then with a serial bit adder, so.. if you mean those, yes?

jjoonathan 6y ago
I mean can you find the bit adder figures for, say, TSMC N7 or N5? I poked around google scholar and wikipedia for a few minutes before giving up and hoping that someone up with the times would know exactly where to look.
- mlyle 6y ago
  No. Those are subject to NDA, but are broadly similar in fmax and prop time under reasonable voltages. I think it's exciting here that they're dicking around with new technologies in their infancy, and in a few coarse design changes of cells went from 60% of CMOS leading edge to about the same numbers. Of course, total system power, etc, is atrocious, considering that this is cryogenic, etc. You need a lot of logic before this could come ahead in efficiency.
  - jjoonathan 6y ago
    > No. Those are subject to NDA Yeah, that's what I thought and why I settled for a less accurate comparison. > I think it's exciting I think it's exciting, too. The extent of my claims is "no, this does not mean 100GHz LN2 CPUs in a few years." I did not intend these remarks to be meaningful to chip designers, only to CPU consumers who see "GHz" and think "CPU clock speeds." The leverage of having a slightly better fundamental device is extraordinary. We should spare no expense looking for them and leave no stone unturned.