2 ms·

Caches are already closer than 3cm and can take multiple cycles to fetch from. DRAM takes 100s of clock cycles to fetch from! It's bad -- but the badness was al

Caches are already closer than 3cm and can take multiple cycles to fetch from. DRAM takes 100s of clock cycles to fetch from! It's bad -- but the badness was already here. Propagation delay problems are real, but for caches IIRC the biggest problems are transmission lines being lossy and having propagation speeds much slower than the speed of light in a vacuum, and for DRAM the biggest problems are waiting for precharge and waiting for the sense amplifiers to stabilize. Waiting for the precision required to read obscenely small capacitors, in other words. If DRAM is 1T1C and SRAM is 6T, I always wondered why we couldn't just have DIMMs of SRAM at 1/3rd the capacity or whatever. Overprovisioning DRAM by that factor is already common, wouldn't eliminating all the downtime be a way to put that slack to work? Like the HDD -> SSD transition? Ah well, I'm sure there's a constraint I'm just not thinking of.

simcop2387 6y ago
You'd need a different CPU these days since the memory controller for sram would be a bit different. That said you do see sram in smaller embedded systems because it's also easier to drive and work with signal wise. I bet someone's done it as a research project with larger CPUs but I bet the cost of the SRAM and the cost of a niche cpu design just made it all not viable in the market place.
- jjoonathan 6y ago
  Right, memory controllers wouldn't be able to fully leverage SRAM DIMMs right out of the gate, but they would be able to partially leverage them right out of the gate and fully leverage them within a JEDEC cycle. It has been multiple JEDEC cycles since over-provisioning became common, so I suspect there must be something else preventing this. SRAM costs way more, but afaik that's an artifact of market size, not fundamental. Hence the 1T1C vs 6T comparison to tease out the fundamental cost difference, which looks to be not worse than 3x-6x more expensive, which would put SRAM DIMMs will within reach. I lean on heinously expensive SRAM in my own embedded designs and would really like to see some market scale drive down those costs!
lowbloodsugar 6y ago
I was going to be really disappointed if this page's comments didn't involve the word "capacitor" at some point.

simcop2387 6y ago

You'd need a different CPU these days since the memory controller for sram would be a bit different. That said you do see sram in smaller embedded systems because it's also easier to drive and work with signal wise. I bet someone's done it as a research project with larger CPUs but I bet the cost of the SRAM and the cost of a niche cpu design just made it all not viable in the market place.

jjoonathan 6y ago
Right, memory controllers wouldn't be able to fully leverage SRAM DIMMs right out of the gate, but they would be able to partially leverage them right out of the gate and fully leverage them within a JEDEC cycle. It has been multiple JEDEC cycles since over-provisioning became common, so I suspect there must be something else preventing this. SRAM costs way more, but afaik that's an artifact of market size, not fundamental. Hence the 1T1C vs 6T comparison to tease out the fundamental cost difference, which looks to be not worse than 3x-6x more expensive, which would put SRAM DIMMs will within reach. I lean on heinously expensive SRAM in my own embedded designs and would really like to see some market scale drive down those costs!

lowbloodsugar 6y ago

I was going to be really disappointed if this page's comments didn't involve the word "capacitor" at some point.