4 ms·
Amplifying your point, μops are grouped into Ways and Ways are 6 μops on Intel and 8 μops on AMD. Ways have constraints; violating a constraint will necessitate
by CalChris 6y ago
Amplifying your point, μops are grouped into Ways and Ways are 6 μops on Intel and 8 μops on AMD. Ways have constraints; violating a constraint will necessitate a spill.
stage bypass
macro + micro fusion
μops
μop Way
functional unit
Loop Stream Detector
16B decoder fetch line
64B instruction cache line
instruction cache
page
DRAM
Picking the right register might occasionally help with a decoder fetch line here and there, and progressively less often with the following instruction packing scenarios. But the first 6 are more important for performance although Intel spends a lot of transistors and dollars to make that less of an issue. They also have nothing (IIRC) with register names.
- fctorial 6y agoIs this documented somewhere? Where do I look if I want more information about uops?
- CalChris 6y agoThere is a new book out, Performance Analysis and Tuning on Modern CPUs, Denis Bakhvalov [1]. Let's be honest; he works for Intel and that should have been Intel CPUs. He's a good writer. Of course, there's Agner Fog's Microarchitecture and the Intel® 64 and IA-32 Architectures Optimization Reference Manual. There are about 11 people who really understand this stuff and they all know each other, and we all read them. Travis Downs and Geoff Langdale (Hyperscan) come to mind. [1] easyperf.net
- vlovich123 6y agoI’ve never seen this detailed high level breakdown before so super helpful, thanks! What’s the difference between page and DRAM? In fact, I probably can only guess at most of these so if you could provide definitions that would be good (or are there Wikipedia pages on all these?)
- jcranmer 6y agoExtra pages use more TLB resources is I think the message GP is trying to convey here.