Essentially all von Neumann architectures have different sizes for code and data. Von Neumann's own IAS, for example, packed two instructions in each data word.

Essentially all von Neumann architectures have different sizes for code and data. Von Neumann's own IAS, for example, packed two instructions in each data word. Even many machines that started out with one instruction per data word (ARM, MIPS, Nova...) eventually evolved to larger data words while keeping the same instruction size. An exception was the PDP-8, but there might have been others. The IBM 360 had 32 bit data words but instructions were 16, 32 and 48 bits long. A modern example is RISC-V. A RV64GC chip, for example, has 64 bit data words but the instructions are 32 and 16 bits wide.