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The data path is 1 bit, but instructions are 4 bits, so it has 16 different instructions. Many processors back then had completely different widths for instruct
by kens 6y ago
The data path is 1 bit, but instructions are 4 bits, so it has 16 different instructions. Many processors back then had completely different widths for instructions vs data.
- colejohnson66 6y agoEven today, Harvard architectures[a] like the PIC have different instruction and data widths. For example, the PIC12 has 12-bit code words with 8-bit data words IIRC. [a]: Are there von Neumann architectures with different width code and data?
- kens 6y agoThe Intel iAPX 432 used variable bit length instructions, where instruction lengths could be pretty much anything, completely unaligned with bytes. As you might expect, this was kind of a mess. The iAPX 432 was designed to be Intel's revolutionary follow-on processor to the 8080 with all sorts of bizarre features such as objects implemented in hardware. However, it fell behind schedule, so Intel created the 8086 as a stopgap processor until the iAPX 432 was ready. Things didn't turn out as expected; the 8086 took over the world and the iAPX 432 was a failure.
- jecel 6y agoEssentially all von Neumann architectures have different sizes for code and data. Von Neumann's own IAS, for example, packed two instructions in each data word. Even many machines that started out with one instruction per data word (ARM, MIPS, Nova...) eventually evolved to larger data words while keeping the same instruction size. An exception was the PDP-8, but there might have been others. The IBM 360 had 32 bit data words but instructions were 16, 32 and 48 bits long. A modern example is RISC-V. A RV64GC chip, for example, has 64 bit data words but the instructions are 32 and 16 bits wide.
- guerrilla 6y agoWell x86-32 varies in width from 1 to 16. I'm not sure about x86-64.
- jlokier 6y agoIt's still true today. The ubiquitous 64-bit ARM has 32-bit instructions and 64-bit data registers.