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My understanding was that RISC-V was created as a teaching tool at Berkley so that students and researchers could have a completely open and modern architecture

• hajile 6y ago
  There’s other reasons. Let’s say you’re building a Larabee-style GPU. You want a simple core with a large set of SIMD units (along with some custom extensions for the hardcoded parts of the pipeline). Adding a multiplier and divider to your core would kill its usability either by becoming non-standard or by wasting huge amounts of space and time. Multiplications and divisions happen out of band on most chips (that is, on the side) because they take so many clock cycles to complete. All the extra synchronization takes a lot of extra work. The RISCV ISA is seeing an uptick in the embedded space where it can be very efficient in core size and thus cost. Here too, requiring those units would hurt the market. Meanwhile, it can reasonably be assumed that any desktop-grade CPU will have those extensions just like it’s assumed that desktop x86 chips all have SSE. Speaking of that, there are over twenty x86 extensions released since 2000. There are 8 or so in just the last 5 years. Despite this, life goes on because the tools that make handing this easy have existed for decades.