RISC-V is targeting embedded customized chips and research and does quite well in that area. In that area sometimes having easier design is much more worth the

RISC-V is targeting embedded customized chips and research and does quite well in that area. In that area sometimes having easier design is much more worth then putting certain optimizations into the ISA spec. But from what _I_ know RSIC-V is neither targeting nor suited for general purpose computing, like general purpose servers, desktops and any phone/tablet but low end ones. The reasons for this are manifold, including manny thinks I can't assess and thinks like that for such targets you like want a bunch of changes. Like e.g. requiring support of one load between a LR/SC pair which might be required to be based on the LR. But then if it would have targeted general purpose computing platforms I believe it would have failed. The fact that RISC-V allows extremely simple implementations is what makes it successful I guess. So they just need to bring out a tweaked RISC-V spec which requires more ISA extensions, more support for LR/SC and similar and maybe does also some ISA changes and voila we it can move into that space, likely reusing a good amount of tooling.