I think RISC-V is converging on a standard “this is what a ‘big’ core looks like”, but with the possibility that you stick a tiny RISC-V core on an IC somewhere

I think RISC-V is converging on a standard “this is what a ‘big’ core looks like”, but with the possibility that you stick a tiny RISC-V core on an IC somewhere. Hardware enumeration IMO can be harder than dealing with ISA variations. (And to my knowledge, RISC-V hasn’t solved any hardware enumeration problems.)